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EagleAutodesk
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SEEED XAIO RP2040 ADC and Buffer Board
The SEEED XAIO RP2040 is a fantastic little dev board, featuring the RP2040 MCU.
I needed a buffered and clamped 12 bit ADC for a volt-per-octave AD9833 based audio voltage controlled oscillator (VCO) I have completed.....The MCU driven VCO works--see the blog post here: https://audiodiwhy.blogspot.com/2023/03/ad9833-voltoctave-vco-new-jacks-n-pots.html; at its core the VCO uses the board you see here.
The op amp elements of this PCB were inspired by the buffering used by Mutable Instrument's famous designs.
The board's additional 12 bit ADC does not suffer from the RP2040's infamous DNL errors present in its ADC/mux subcircuit. So if you need a 12 bit ADC for your design that is better than the ADC built into the RP2040 this might be a good solution.
CALIBRATION--Volt per octave (synthesizer) values.
The associated resistors for MCP6004 stage U1A allow you to precisely dial in the source voltage going into the MCP3201 ADC. For audio synthesizer volt per octave applications--the AD9833 based synth VCO for example, I successfully used a 50K 25 turn trimmer for the T1, 47K 1% for R8, 100K 1% for R5, and 22K 1% for R6. I put T1 into the middle of its travel and adjusted until I got an acceptable 7 octave range.
For other applications, please choose resistors surrounding U1B (R4, R3, R11), U1C (R1, R8, R10), and U1D (R12, R13, R2) to fit your needs.
USING THE BOARD:
Please note that voltages delivered to the RP2040 MCU by the bufffers are inverted to lower parts count in the best Mutable tradition.
If you use this board in one of your designs, your software will have to accommodate this voltage inversion.
You can add 100 mil jumpers to JD0, JD1, and JD2 to buffer the RP2040's ADC0,1 or 2's inputs or leave the jumpers off to use pins D0, D1 and D2 on the breakout board's edge connectors for GPIO.
If you don't use an op amp channel, please consider providing its input with a small voltage (say 500mV) so the Op amp stage doesn't go to its rail at output. You probably won't blow anything up if you just let unused inputs float, but managing unused op amp stages correctly is considered a best practice in analog design--learn more from the video here.
Alternately, if you have omitted JD0, 1, and/or 2, you can leave C6/R10 (ADC0); C7/R11 (ADC1); and/or C8/R12 (ADC2) off the PCB. In this configuration, the unused buffer will get the zener's approximate -10V signal which will keep the unused stage from flopping around at its output.
The board requires +/- 12V, and will probably work fine with +/- 15V, but to date I have only tested the board with Eurorack voltages (+/- 12V)
Current draw for the board without CV in is about 40mA.
There is a 5V voltage regulator on this buffer board, as well as a 3.3V rail brought to an edge connector, provided by an HT7333 LDO regulator.
The HT7333 can provide up to 250mA of current at 3.3V for external components, but I'd recommend sourcing less than that (probably not more than 100mA), and/or putting a heat sink on the HT7333 as needed.
The board provides 3.3V volt clamps for the RP2040's ADC inputs, but please still be cautious with your input voltages and buffer resistor values. Voltages greater than 3.3VDC presented to an RP2040 can ruin an MCU input pin or worse, so I recommend testing your buffered ADC inputs with a voltmeter before dropping in your SEEED RP2040 board.
For more detail, please see these Audio DIWHY blog posts:
https://audiodiwhy.blogspot.com/2023/01/improved-seeed-rp2040-buffer-board.html
https://audiodiwhy.blogspot.com/2022/10/ad9833-rp2040-vco-voltoctave-is-working.html
Revisions:
4-22-23 made signal flow from JP1 to ADC1 consistent with JP0 > ADC0 and JP2 > ADC2.
5-20-23 replaced 3.3V Zener with L7333 regulator--provides better consistency of 3.3V output for external loads
5-20-23 brought 3.3V regulated voltage from RP2040 to a test point on the board. The 3.3V edge connector pin is now sourced from the 7333 regulator instead of the 3.3V regulator on the SEEED board.
SEEED XAIO RP2040 ADC and Buffer Board
*PCBWay community is a shared platform and we are not responsible for any design issues.
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