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How to Select the Right HDI Stack-Up at the HDI Design Stage

by: Jan 07,2026 532 Views 0 Comments Posted in PCB Design & Layout

HDI PCB Design PCB HDI HDI board design HDI PCB layout HDI PCB design guidelines

Stack-Up Determines Everything

Once the PCB stack-up is defined, nearly 80% of the total manufacturing cost is effectively locked in. This is especially true for HDI PCB design, where stack-up decisions directly determine the build-up structure, microvia configuration, and overall process complexity.


Start with Routing Requirements, Not Manufacturing

Stack-up selection should always start from routing requirements, rather than being constrained by manufacturing considerations too early. There is no need to select a high-level HDI structure at the beginning. While it may seem “safer,” the cost will increase rapidly. The stack-up only needs to meet the actual design requirements—nothing more.

At the design stage, the first step is to determine the minimum HDI level required to complete routing. This decision should be based on the following key factors:

  • BGA pitch: How dense are the pins? Ball pitch directly determines fan-out difficulty and is the primary reference when selecting the HDI level.
  • I/O count: How many signals need to be routed out? Higher I/O density places greater demands on via structures and routing layers.
  • Target trace width / spacing: How fine do the traces need to be? Whether 3/3 mil routing is acceptable or 2/2 mil is required has a direct impact on the HDI level selection.


Practical examples:

  • BGA pitch ≥ 0.8 mm: Standard through-hole technology is usually sufficient, or a low-cost first-order HDI (1+N+1).
  • BGA pitch ≈ 0.5 mm: First-order HDI (1+N+1) is typically required. For very high I/O counts, second-order HDI (2+N+2) may be necessary.
  • BGA pitch ≤ 0.4 mm: Any-layer HDI is often unavoidable. At this level, extreme caution is required, as both cost and manufacturing complexity increase significantly.


HDI Stack-Up Selection Flow

1.Define routing density

This is the starting point of requirement analysis. The following aspects should be clearly defined to determine whether HDI is required and how many build-up layers may be needed:

  • Critical components: Which BGA has the smallest pitch?
  • Signal quantity: How many signals must be routed out, especially high-speed signals?
  • Physical constraints: What are the allowed board thickness and dimensions?


2.Evaluate fan-out feasibility

After determining routing density, evaluate whether BGA fan-out is feasible:

  • Fan-out trial: With the target trace width and spacing, can at least one trace be routed between BGA pads?
  • Channel calculation: Using first-order HDI (laser vias on outer layers only), what percentage of pins can be successfully fanned out? How should the remaining pins be handled?
  • Key question: Can the planned layer count and via types provide sufficient routing channels?

If fan-out can be completed at a lower HDI level, a simpler structure should always be preferred.


3.Select minimum HDI level

Based on the conclusions from the previous steps, select the simplest and most cost-effective structure that meets the requirements. Performance only needs to meet design targets—overdesign should be avoided.

  • Prioritize through-hole or first-order HDI
  • If first-order HDI is insufficient, consider buried vias or second-order HDI
  • Only consider any-layer HDI when lower-level structures cannot support routing, particularly for extremely fine-pitch (≤0.4 mm) and high-pin-count BGAs


4.Confirm with PCB manufacturer

Once the stack-up is defined, it should be confirmed with the HDI PCB manufacturer to ensure feasibility. Early DFM verification during the design stage helps avoid redesigns, board revisions, and mass-production risks. You can consult PCBWay regarding manufacturing capabilities to assist in completing your HDI design.


Reliability-Driven Stack-Up Design

  • Prioritize Staggered Microvia

Staggered microvias are offset between adjacent layers rather than aligned vertically. This structure distributes stress more evenly during thermal expansion or board bending. For applications with high reliability requirements or frequent thermal cycling, staggered microvias should be prioritized.

  • Control Microvia Aspect Ratio

Excessive aspect ratios make it difficult for plating solutions to uniformly coat the via walls, leading to uneven copper thickness or voids. This severely impacts both electrical reliability and mechanical strength. Proper dielectric thickness and build-up planning are essential to keep microvia aspect ratios within a stable manufacturing window.

  • Minimize the Use of Stacked Vias

As the number of stacked vias increases, accumulated stress concentration and CTE mismatch risks rise sharply, and failure probability increases exponentially. Stacked vias should therefore be minimized whenever possible.

  • Optimize Build-Up Layer Placement

Asymmetrical stack-ups can introduce uneven stress during lamination, increasing the risk of warpage. This affects both manufacturability and long-term reliability. In high-speed or high-current areas, build-up layer placement should be planned by balancing electrical performance and mechanical reliability


Cost-Aware HDI Stack-Up Design

  • Lamination Cycles Are Cost Multipliers

Each lamination cycle is a complete manufacturing process involving lamination, drilling, and plating. The HDI “order” (1st order, 2nd order, or any-layer) directly determines the minimum number of lamination cycles required. Every additional cycle increases lead time, material consumption, and yield loss risk. Lamination count is one of the most significant cost drivers in HDI PCB fabrication.

  • Via-in-Pad Is Not Always Necessary

Via-in-pad requires additional resin filling and planarization processes, with extremely high requirements for precision and materials. This significantly increases manufacturing cost and should only be used when absolutely necessary.


Common HDI Stack-Up Design Mistakes

  • Choosing Any-Layer HDI “ for Safe

Selecting any-layer HDI at the initial design stage purely for safety often results in a dramatic cost increase. Designers should always start with the lowest-cost structure and only upgrade when core routing requirements cannot be met.

  • Failing to Confirm Mass Production Capability

Designs that are not verified with the manufacturer may turn out to be unbuildable, requiring major redesigns. After defining a preliminary stack-up, it is essential to communicate with the PCBWay factory to ensure manufacturability.

  • Ignoring Thermal Stress Concentration

Focusing only on electrical performance while using excessive stacked vias can lead to severe stress concentration due to CTE mismatch between materials. This often causes copper cracking or delamination. Designers should prioritize staggered vias over vertically stacked vias and proactively add thermal vias in high-power areas to distribute and dissipate heat.


Conclusion

The core of HDI lamination design is to achieve an optimal balance between performance, reliability, and cost. Designers should focus on realizing product functionality through the simplest and most manufacturable structures possible. By controlling complexity at the lamination stage, HDI PCB designs can significantly improve manufacturing yield, reduce production risks, and ensure long-term product stability.

Feel free to ask PCBWay HDI Manufacturer to help your design be better!

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