This is just sharing the project from https://github.com/rabs664/Amstrad-CPC-Pico-Logic-Anlyser-Interface – all design credit goes to its author, Rabs (rabs664). It is a backplane for the Amstrad CPC expansion bus that maps all 47 bus signals onto two gusmanb Pico Logic Analysers. The master analyser captures the Z80 clock, control lines, data bus and upper address lines. The slave captures the lower address lines and the CPC-specific control signals.

The 2-layer, 66 × 80 mm board has card-edge gold fingers at both ends, so the bus passes straight through to further expansions. A jumper lets the CPC power both analysers, with Schottky diodes guarding against back-powering. Assembly is simple: six through-hole parts – two 2×16 sockets, two 1N5819 diodes, a 22 µF capacitor and a jumper header.

The author reports testing it on an Amstrad CPC 6128, and the KiCad project, gerbers and schematic are released under GPL-3.0. As the original project warns, use it at your own risk.