Introduction

I know, this is not the first TTL CPU/Computer and not the last. But I got interested in designing my own TTL-CPU after a friend showed me his "Ben Eater 8bit Computer" setup. I really liked the educational part of it, even though the CPU is very limited. I then looked into the "Gigatron - TTL microcomputer", which is a clever RISC-like design.

Both CPU designs had not been modeled after any existing CPU architecture. Because of its nature, the Gigatron doesn't even require any micro code. It runs fast, but it also doesn't support any register display. Ben Eater's design supports binary and hex-displays, but is very limited and slow.

For my own design I wanted to imitate a real existing CPU, allowing for extensive debug and display options as well as running it as fast as the original. A simple and very common CPU of the past was the MOS 6502 with its variant 6510 running in the Commodore C64. Even though I liked Zilog, the complexity of the Z80 CPU was much higher and harder to bring on a board like this. However, here is a project that implements both if of interest: Isetta TTL computer

To allow for extensive register displays, I added headers where smaller boards can be plugged in for single step updates. They can be removed for full speed. A special logic also allows single instruction steps, single clock phase steps. For the last mode I found it better to replace the 8-bit hex display boards for the instruction register and the micro codes with special LCD module controllers displaying text lines in addition to the codes.

I tried to stick to 74xx logic chips, mainly the HCT series. But I had to do some exceptions. I wanted to use real ALU chips (because I always wanted to do something with these) and had to settle to the 74LS181, which is still available. I also had to use two GALs, one for the C64-like chip select decoder for memories and IOs (part of a PAL in the C64). And I had to introduce the second GAL for remapping the ALU codes because I ran out of micro code bits. Now it maps 4-bit codes plus CY to 5 ALU selection bits plus carry-in. I had to resist the temptation to replace more logic with GALs. The extreme would have been implementing the whole board into an FPGA, which was not the goal :-).

The goal was to create a design that comes as close to the internal processor functionality as possible, including timing. Since the hardware is not exactly the same, the micro code execution does not match 100%. But the general execution comes close and all instructions take the same number of clocks as the original. In very few cases dummy micro steps had to be included to meet the target. The only exceptions, where the original timing could not be met, are the ADC and SBC instructions in BCD mode. As far as I could find out, these are seldomly used, so this mode was implemented with more micro steps instead of more hardware.

There is a great chip simulator here.

Before I even got started designing my own CPU, I spent quite some time on creating a simulation tool SimTTL to analyze both designs above and then working on this design. In addition, I had to create the MicroCodeGenerator for this design and the small boards HexDisplayController, LCD-DisplayController and ArduinoExpander (for testing bread board circuits). All of this came together in this project.

If you want to know more about the 6502 processor, there is a lot out there. I personally liked 6502.org and masswerk and many more.

One more info: I used this programmer for GALs and Flashs.