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ESD Inhibition Criteria in PCB Design

by: Sep 14,2018 262 Views 0 Comments Posted in PCB Design & Layout

Charge Injection Electrostatic discharge PCB design ESD

Introduction:

Electrostatic discharge (ESD) is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. A buildup of static electricity can be caused by tribocharging or by electrostatic induction. The ESD occurs when differently-charged objects are brought close together or when the dielectric between them breaks down, often creating a visible spark. ESD can create spectacular electric sparks (lightning, with the accompanying sound of thunder, is a large-scale ESD event), but also less dramatic forms which may be neither seen nor heard, yet still be large enough to cause damage to sensitive electronic devices. Electric sparks require a field strength above approximately 40 kV/cm in air, as notably occurs in lightning strikes. Other forms of ESD include corona discharge from sharp electrodes and brush discharge from blunt electrodes. ESD can cause harmful effects of importance in industry, including explosions in gas, fuel vapor and coal dust, as well as failure of solid state electronics components such as integrated circuits. These can suffer permanent damage when subjected to high voltages. Electronics manufacturers therefore establish electrostatic protective areas free of static, using measures to prevent charging, such as avoiding highly charging materials and measures to remove static such as grounding human workers, providing antistatic devices, and controlling humidity. ESD simulators may be used to test electronic devices, for example with a human body model or a charged device model.

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PCB design can reduce the unnecessary cost of troubleshooting and rework. In the PCB design, transient voltage suppressor (TVS) diode is used to inhibit direct charge injection caused by ESD discharge, so it is more important to overcome EMI electromagnetic field effect caused by discharge current. This article will provide PCB design guidelines that can optimize ESD protection.

Circuit loop:

 

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(Figure 1)

Current is induced into circuit loops that are closed and have varying magnetic flux. The amplitude of the current should be proportional to the area of the loop, that is to say, the area of the loop must be reduced because the larger loop contains more magnetic flux, which induces a stronger current in the circuit. The most common loop is shown in figure 1, which is formed by power supply and ground wire. Where possible, a multilayer PCB design with a power source and an interface layer can be used. The multilayer circuit board not only minimizes the loop area between power supply and ground, but also reduces the high-frequency EMI electromagnetic field generated by ESD pulse. If the multilayer circuit board cannot be used, the wire used for power and grounding must be connected to a grid as shown in figure 2.

 

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(Figure 2)

 

 

Grid connection can play the role of power supply and ground layer. The printing lines of each layer are connected with via holes and the spacing of the connection between via holes should be within 6 cm in each direction. In addition, when wiring, the power supply and the grounding printed wires as close as possible can also reduce the area of the loop, as shown in figure 3:

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(Figure 3)

Another way to reduce loop area and induced current is to reduce parallel pathways between interconnected devices, as shown in figure 4.

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(Figure 4)

When more than 30cm of signal connection line must be used, protective line can be used, as shown in figure 5.

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(Figure 5)

A better approach is to place the ground signal line near the signal line within 13mm of the protection line or the ground line layer as shown in figure 6. The long signal line (> 30cm) of each sensor or the power line is intersected with the ground line.

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(Figure 6)

About the length of the lines:

The long signal line can also become the antenna receiving ESD impulse energy. The use of shorter signal line can reduce the efficiency of signal line as the antenna receiving ESD electromagnetic field. Interconnect devices in adjacent locations to reduce the length of the interconnect printed line.

 

Charge Injection:

Direct discharge of ESD to ground layer may damage sensitive circuit. Thus, it would be better to use one or more high frequency bypass capacitors placed between the power supply and the ground of the vulnerable components when using the TVS diodes. The by-pass capacitance reduces charge injection and maintains the voltage difference between the source and the ground port. TVS shunt the induced current and keep the voltage difference between the tong space of TVS. TVS and capacitors should be placed as close as possible to the protected IC (see figure 7) to ensure the shortest road from TVS to the ground and the length of the capacitor pin to reduce parasitic inductance effect.

 

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(Figure 7)

The connector must be mounted to the copper layer on the PCB. Ideally, the copper layer must be isolated from the PCB's contact layer and connected to the pad through a short wire.

Other Rules of PCB Design:

1. Avoid important signal lines being at the edge of the PCB such as clocks and reset signals;

2. Set the unused portion of the PCB to ground plane;

3. The ground wire of the main case should be at least 4 mm apart from the signal line;

4. Keep the length/width ratio of the ground wire of the main case less than 5:1 to reduce the inductance effect;

5. Protect all external connections with TVS diodes.

 

Protect Parasitic Inductance in Circuits:

Parasitic inductance in the TVS diode path will produce severe overshoot voltage when ESD event occurs. Despite the TVS diode, due to the induced voltage (VL=L x di/dt) at both ends of the inductive load, a high overshoot voltage may still exceed the damaged voltage threshold of the protected IC.

The total voltage borne by the protection circuit is the sum of the clamp voltage of TVS diode and the parasitic inductance (VT=VC+VL). An ESD transient induced current can peak within a period of less than 1ns (according to IEC 61000-4-2 standard). It is assumed that the lead inductance is 20nH per inch, the line length is 1/4 inch, and the overshoot voltage will be a pulse of 50V/10A. The rule of thumb is to design the shunt path as short as possible to reduce the parasitic inductance effect. All inductive pathways must be considered with a ground loop, the pathways between TVS and the protected signal lines as well as the pathways between connectors to TVS devices. The protected signal line should be connected directly to the ground surface. If it is not connected to the ground, the connection of the ground loop should be as short as possible. The distance between the ground of the TVS diode and the receiving point of the protected circuit should be as short as possible to reduce parasitic inductance on the ground plane. Finally, TVS devices should be as close to connectors as possible to reduce transient coupling into nearby lines. Although there is no direct access to the connector, this secondary radiation effect can also disrupt the work of other parts of the circuit board.


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