1. Blog>
  2. Taking a look at how to create ESP8266 from PCB level also taking EMC regulations into consideration

Taking a look at how to create ESP8266 from PCB level also taking EMC regulations into consideration

by: Jul 01,2024 889 Views 0 Comments Posted in PCB Design & Layout

PCB layout PCB Design KiCAD CircuitMaker

In this article, I will be sharing with you the way the ESP8266EX is made from PCB level.


This was done using the PCB software known as Kicad. I used the ESP8266 datasheet to understand the connection between components. The schematic is as follows:

Now looking at each section:

  1. Flash

It creates a voltage divider network with the parasitic capacitance of the trace and the pin. This voltage divider network reduces the voltage swing on the SD_CLK pin and consequently reduces the cross-talk.


Crystal Oscillator

The crystal oscillator is used to provide stable and precise clock signal that is then used for the proper operation of digital devices. It is connected to the ESP8266EX microcontroller through pin 27 and 28. They have capacitors which are grounded. The capacitors are grounded so as to provide a stable reference voltage and filter out unwanted noise.To add on, it provides a path of low-impedance to the ground for high freq noise and interference.This reduces EMI. The values of the two capacitors can be flexible, ranging from 6pF to 22pF, however, the specific capacitive values of C1 and C2 depend on further testing and adjustment on the overall performance of the whole circuit. Normally, the capacitive values of C1 and C2 are within 10pF if the crystal oscillator frequency is 26MHz, while the values of C1 and C2 are 10pF<22pF if the crystal oscillator frequency is 40MHz.

RF section

According to my RF classes, matching is making the input resistance equal to the load resistance. If the antenna is approaching 50 ohms then no matching is required since the output impedance of pin 2 is 50 ohms. However cheap antennas do not have 50 ohms impedance, so the N – type matching is there to help with the matching.

The resistance measured at the terminals of the antenna accounts for the power that is radiated from the antenna which is primarily the “radiation resistance”.

Antenna exhibits two types of noise:

i)                   Thermal noise generated from ohmic resistance

ii)                  The noise received from external sources (anybody with Temperature greater then 0K radiates noise energy). This is known as noise temperature.

  where Ta = noise temeperature

                                      V = noise voltage

                                      R = resistance of the antenna

                                      B = Bandwidth


Component Placement, Routing and EMC Regulations

From my electronics lecture, I learnt that when designing a system, the only point we have control over EMI is at the PCB level. At this stage, I tried to look at EMC regulations whilst placing my choosing number of layers, component placing and doing the signal routing.

Here is the overview of the board after the whole process:

The circuit board operates at high frequency , hence I used multiple grounding. We know that at high frequencies return current follows the path with minimum inductance because inductance cause a delay in the flow of return current.I kept this in mind during the component placement and routing part. To get this point we have to know the relationship between Inductance and Frequency which is given by this formulae :

For EMI to occur we need a RF source, a receiver that is easily disrupted and also a coupling path that is either conductive or inductive. In my case, the RF source is the RF antenna, the "susceptible" receiver is the microcontroller module "ESP8266EX" and lastly the coupling path are the high speed digital signal traces. So the best methed is to keep the RF and Crystal Oscillator far from each other.

This is a four layer board. The layers details are as follows:

1.     First layer: signal lines and components are placed here.

2.     Second layer: GND layer and no signal lines are placed here. Vias are used to connect GND signals in other layers.

3.     Third layer: Pwr layer. Only power signals allowed. Vias also used to connect to power pins of components.

4.     Bottom layer: Used for signal lines only.



Power Supply

Power lines placed on the third layer. When the power lines reached the pins of the chipset, VIAs are needed so that the power lines can go through the layers to connect the pins of the chipset on the TOP layer.

Crystal Oscillator

This part is very crucial. The placement of this circuit in our board. A crystal oscillator use mechanical resonace of a vibrating piezoelectric material to create electrical signal with very precise frequency. I avoided placing high digital signal traces under the crystal oscillator because this avoids EMI and RFI which can cause the crystal to vibrate irregularly. This would result to inaccurate frequency from the oscillator. I aso placed the oscillator close to the XTAL PIns, ensuring the traces are short. Short traces means it lowers the impedance of the traces. This then gives an effictive return path for the return current. The capacitors are also close to the oscillator as this reduces any risk of any parasitic capacitance or inductance that may be in the signal path. They are also grounded so as to help filter out noise and reduce EMI.

RF section

RF lines connecting the chip and antenna are not covering drills because this may cause discontiunity in the return path of the return current. RF antenna placed be set away from crystal oscillators. RF lines not set at a 45 degree angle because any sudden change in direction can create impedance mismatches and cause signal reflection). No signal lines of high frequency are set near RF lines.

3D View

Schematic and Layout
Join us
Wanna be a dedicated PCBWay writer? We definately look forward to having you with us.
  • Comments(0)
You can only upload 1 files in total. Each file cannot exceed 2MB. Supports JPG, JPEG, GIF, PNG, BMP
0 / 10000
    Back to top