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PCB Design Guidelines

by: Jan 25,2014 13372 Views 0 Comments Posted in Engineering Technical

printed circuit board PCB Design

ABSTRACT
General layout guidelines for printed circuit boards (PCB), which exist in relatively obscure documents, are summarized. Some guidelines apply specifically to microcontrollers;
however, the guidelines are intended to be general, and apply to virtually all modern CMOS integrated circuits. This document covers most known and published layout techniques as applied in a low-noise, unshielded environment. Efforts have been made to target two-layer boards, and the maximum acceptable noise level is assumed to be 30 dB, or greater, more stringent than FCC Part 15. This level seems to be the upper limit of acceptable noise in European and U.S. automotive markets. This document does not always explain the why’s of a given technique because it is intended only as a reference document, not a teaching aid. The reader is cautioned against making the assumption that although on a prior design a given technique was not applied and the unit had acceptable performance, that the technique is not useful. Over time, as IC devices increase in speed and density, every method to isolate and reduce noise will be required.

1 Background
1.1 RF Sources
Design guidelines to be discussed concern radio-frequency (RF) noise from the microcomputer. This noise is generated inside the device and is coupled out in many different
possible ways. The noise is present on all outputs, inputs, power supply, and ground at all times. Potentially, every pin on the microcomputer can be a problem. The biggest problem is noise from the integrated-circuit (IC) input/output (I/O) pins. Because the area covered by traces connected to them on the PCB form a large antenna. These pins also connect to both internal and external cables. The noise from clock switching within the IC appears as ‘‘glitches” on a static output. The glitch is caused by the common impedance of the output pin and the clock drivers, that is, the shared pins that supply each power and ground. The synchronous nature of most devices causes all current-switching events to occur at the same time, making a large noise spike containing RF energy.

The second most-important contributor is the power-supply system, which includes the voltage regulation and the bypassing capacitors at both the regulator and at the microcomputer. These circuits are the source of all the RF energy in the system, as they feed the clocked circuits inside the IC with the current required for switching. The third noise source is the oscillator circuit, where the oscillator swings rail to rail. In addition to the fundamental frequency, harmonics are introduced on the output side because the output buffer is digital, which squares the sine wave. Also, any noise caused by internal operations, such as the clock buffers, appears on the output. If proper separation is maintained between the crystal and its tank circuits from other components and traces on the PCB, and the loop areas are kept small, there should be no problems with this noise source. But it has been shown that if ICs or passive components, such as the main VBatt series inductor, are placed close to the crystal, harmonics of the crystal can couple and propagate.

The primary focus in this application report is on the first and second previously described noise sources. The way to deal with the third noise source has been addressed. Also, critical information is disclosed on board zoning (floor planning) and shielding.

1.2 Surface-Mount Devices vs Through-Hole Components
Surface-mount devices (SMD) are better than leaded devices in dealing with RF energy because of the reduced inductances and closer component placements available. The latter is
possible due to the reduced physical dimensions of SMDs. This is critical to two-layer board design, where maximum effectiveness from noise-control components is needed.

Generally, leaded capacitors all go self-resonant (become more inductive than capacitive) at about 80 MHz. Because noise above 80 MHz needs to be controlled, serious questions should be asked if a design is to be executed only with through-hole components.

1.3 Static Pins vs Active Pins vs Inputs
As mentioned previously, all lines have noise from the processor, to some degree. The total noise from a pin depends on how much noise the microcomputer provides it and its
function in the system. For example, an output pin has the noise from the microcomputer’s power rails and the noise capacitively coupled from adjacent pins and the substrate.

If the pin’s function is the system clock, that too is noise. Even if the pin were static at a one or zero level, one would still have to contend with noise from inside the chip. In the case of an I/O pin in the input mode, the capacitance of the unused output transistors transfers noise from both power rails to the pin. The amount of noise is based on the impedance of whatever is connected to the pin. The higher the impedance, the more noise comes out of the microcomputer. That is why unused inputs should be tied to the lowest-impedance rail: ground, by direct short, if possible.

With respect to switching output signals, basically, only worry about signals that make an edge transition at a rate greater than 50 kHz (see Figure 1). If a pin changes its state at a rate of less than once per 100 instructions, this is acceptable because the contribution from switching is negligible. If the pin toggles, and toggles back on the next instruction, and remains static for 100 instructions, it, too, is acceptable because it contains the same amount of energy as in the previous example.


1.4 Basic Loops
Every edge transition that is sent from the microcomputer to another chip is a current pulse. The current pulse goes to the receiving device, exits through that device’s ground
pin, then returns via the ground traces, to the ground pin of the microcomputer (see Figure 2). The pulse does not exit the ground lead of the receiving device and return to the battery, but travels in a loop to where it originates. Loops exist everywhere. Any noise voltage and its associated current travels the path(s) of lowest impedance back to the place where it was generated. This is a very powerful concept, because it allows you to mitigate noise propagation by controlling the shape and impedance of the return path.

A loop can be a signal and its return path, the bypassing loop between power and ground and the active devices inside the microcomputer, the oscillator crystal and its driver in the microcomputer, as well as the loop from the power supply or voltage regulator to the bypassing capacitors. Other more difficult loops are actually ambient field loops. For example, the crystal itself radiates energy that can be coupled into a wire running nearby. Then, the wire contains noise that tries to get back to the crystal loop. That may involve a very long and convoluted path, which serves as another antenna for noise from the crystal.



1.4.1 Proportionality of Loops and Dipoles
Loops and dipoles are antennas. Their radiating efficiency increases up to 1/4 wavelength (l) of the frequency of interest.
Geometrically, that means, in the case of a loop, nthat the larger the laid-out area of the loop, the stronger the radiation until one or both legs of the loop reach 1/4
wavelength. In the dipole, the longer the antenna, the more radiation, until the length of the antenna reaches 1/4 wavelength. At 1 MHz, 1/4 l = 75 m. At 300 MHz, 1/4 l = 25 cm, or about 10 inches.

1.5 Differential vs Common Mode
Differential-mode noise is the noise of a signal as it travels down its trace to the receiving device, then back along the return path (see Figure 3). There is a differential
voltage between the two wires. This is the type of noise that every signal must make nin order to do its job. Make sure there is no more noise than needed to get the job done, in terms of both frequency content (rise and fall times) and the magnitude of the current. In common mode, a voltage travels down both the signal and return lines at the same time. There is no differential between the signal and its return. The voltage is caused by an impedance that is common to both the signal and the return. Common impedance noise is the most common source of noise in most microcomputer-based systems that are not using external memories.





2 Board Layout
2.1 Grounds and Power
The only non-dc current that should flow in the power routing of the PCB is the current required to replenish the bypassing capacitor. High-frequency current used inside the
microcomputer that is switched on the input clock edges should come from the bypassing capacitors, not from the power supply.

2.1.1 Inductance
Inductance increases with increasing length, and decreases (at a slower rate) with increasing width of the conductor. In power routing, the inductance makes voltage drops that
radiate and propagate. Because it is not desirable for any trace to radiate RF energy, any trace carrying RF energy should be as low an inductance as possible:
• On a two-layer board, for both power and ground, the length-to-width ratio should not exceed 3:1 for any traces
between the IC and the voltage source.
• Power and ground should be run directly over each other, which reduces impedance and minimizes loop area.

2.1.2 Two-Layer vs Four-Layer Boards
A two-layer board can achieve 95% of the effectiveness of a four-layer board by emulating what makes a four-layer board better:
• Make an extra effort to route ground underneath power.
• Grid power and ground, but be careful not to create unneeded common impedance connections or to violate an intended isolation, such as between high-power and digital grounds.
See section 2.2.3, Gridding to Create Planes.
• Route returns for direct connections to the processor I/Os directly under the signal trace. Gridding is a space-effective way of doing this. See section 2.2.3, Gridding to
Create Planes.
• Under the microcomputer, build a solid plane for ground that bypassing components and the oscillator loop can be tied to. Tie this ground to the ground pin and the power-
supply bypass capacitor. This is called a microcomputer ground, which is discussed in section 2.1.3.

2.1.3 Microcomputer Grounds in One- and Two-Layer Designs
A microcomputer ground is a ground area on the bottom layer underneath the microcomputer that becomes a ground island for the noise made by the microcomputer. This area should
extend about 1/4 inch outside the outline of the device and tie to the microprocessor ground. Ground connections for the power-supply bypassing capacitors and any bypassing capacitors on the pins also should tie to this ground. Additionally, the ground area should extend out and around the through holes for the oscillator leads, and the bypass capacitors tied in to provide the smallest possible loop area when viewed from the top. See Figure 4 for an example.



The topside traces are shown in dotted line form on the bottom side diagram for alignment purposes. Notice how the oscillator capacitors lay back over the traces between the
device and the crystal. This eliminates loop area. The same is true for the placement of the ferrite bead and Vcc bypass capacitor, being centrally located with the main power lead running almost directly under the lead finger for the ground.

2.1.4 Signal Return Grounds
As mentioned previously in section 1.4, a loop is made by a signal, and the ground return path from the receiver device back to the signal source. Signal return paths present
the most difficult design problem in PCB layout. It would be difficult to route a ground return underneath each trace connected to a signal pin on the microcomputer. But, this is exactly what the ground plane of a four-layer board does. No matter where the traces run, there is always a ground return path running underneath it.

The closest approximation to having a ground plane in a two-layer board comes from gridding the ground, as described in 2.2.3. As stated previously, radiation from the signal traces is the primary concern. Reducing the loop area by routing the return for the signal underneath the signal trace is most effective way of dealing with this problem. Therefore, creating a ground grid is the most important thing to do (after floor planning) in laying out the PCB.

2.1.5 Analog vs Digital vs High Power
Digital ground and power carry the RF energy that needs to be contained, so it is best to isolate it from any other power and ground, either analog, high power, or other
unrelated trace. If noise from the microcomputer or any other circuit gets on an isolated ground, it can be returned by careful placement of a small RF capacitor in the 470 – 1000 pF range. Choosing the location of the capacitor is by trial and error, and is best done in the screen room.

2.1.6 Analog Power-Supply Pins and Analog Reference Voltages
The reference voltage of an analog-to-digital (A/D) converter integrated into a microcomputer does supply a very small amount of clocked current; however, it is not enough to be
concerned about from a noise-emissions standpoint. Most applications have the analog Vss/Vcc tied to the digital Vss1/Vcc1 pins, which does not change significantly the noise characteristics of the A/D nor the radiated emissions, provided the power distribution is built to guidelines in sections 2.1.1 through 2.1.4.

2.1.7 Power Plane Do’s and Don’ts for Four-Layer Boards
The reasons for reduced noise from four-layer boards were mentioned in section 2.1.2. The following guidelines should maintain the advantages gained in the four-layer board.
• Pay utmost attention to how the holes and cutouts in the planes are done. They break up the plane and, therefore, cause increases in loop areas (see A and B in Figure 5).
• Avoid buried traces in the ground plane. If you have to use them, put them in the +V plane.
• When making through holes for 100-mil-center-spacing leads in the plane, place a small trace between each pin. Breaking up the plane with a row of holes is much better than
having a long slot (see C and D in Figure 5).
• When splitting up the ground plane to make, for example, a digital and power ground, make sure that the signals connected to the microcomputer are still located entirely over
the digital ground. Extending signal traces beyond the power ground hurts because the power ground does not work to reduce the loop area for digital noise signals.



2.2 Power Distribution for Two-Layer Boards
2.2.1 Single-Point vs Multipoint Distribution
In a true single-point power-distribution system, each active component has its own separate power and ground, and these traces would remain separate until they meet at a single reference point. In multipoint systems, the connections are made in a daisy-chain fashion, so there are multiple 0-V reference points. It is clear that multipoint systems have the potential for common impedance coupling. While implementing a single-point system may be impossible, a combination of single point for devices generating RF and multipoint for everything else serves to reduce noise. The best scheme possible has a single point that ties together the regulator ground, microcomputer ground, battery negative, and chassis or shield (see Figure 6).

2.2.2 Star Distribution
Star distribution is much like single point. It looks like all points reference the same fixed point, which is located centrally, by about the same length of traces. Additionally, that same reference point may be attached, via a large single trace, to its source, which is not centrally located. Therefore, the major differences to single point are:
• The single reference point on a star can be a longer trace, instead of a point
• The point where the separate traces begin is near the center of the board, and each trace goes in its own direction, with the resulting trace length equal to that of all the others.
• The star is best applied to something like a system clock in a high-speed computer board. The signal originates on the edge connector and proceeds to the center of the board, where it then splits and goes to each place it is needed. Since it effectively originates at the center of the board, the delay in the signal from one area of the board to another is minimal. The name star sometimes is used to refer to single point, making the above clarification necessary.



2.2.3 Gridding to Create Planes
Gridding is the most critical design technique for two-layer boards. Much like a power utility grid, gridding is a network of orthogonal connections between traces carrying ground. It effectively creates a ground plane, which provides the same noise reduction as on four-layer boards. It serves two purposes:
• Emulates the ground plane of a four-layer board by providing a ground return path under each of the signal traces
• Lowers the impedance between the microcomputer and the voltage regulation

Gridding is done by expanding any ground traces and using ground-fill patterns to create a network of connections to ground across the PCB. For example, a PCB has most of the topside traces running vertically and most of the bottom traces running horizontally (see Figure 7). This already is working against having the return run directly under signal.
First, every ground trace is expanded to fill up as much of the empty PCB space as possible. Then, all the remaining empty space is filled with ground. Place through holes where top-side traces cross bottom-side traces. Then do the same to the ground-fill patterns. Ground-fill patterns make a better contribution to the grid if they are tied to ground at both ends. A ground-fill-pattern geometry connected at only one point is just a ground shield, but if connected at two or more points, it becomes a conductor, and, therefore, becomes
a contributor in the grid.
• Grid as much as possible on a two-layer board. Look for places where small changes in the layout would allow
another connection to be made in the grid.
• Use as many through holes as can physically fit.
• Lines do not have to be orthogonal, or of the same width.



An example of gridding ground only to achieve the effect of a ground plane is shown in Figure 8. Note how the changes made in order to implement this were minor, indicating how a small effort can have a large payback.



In the example in Figure 8, A and B represent the top and bottom sides, respectively, of a simple two-layer board. The +V traces and all interconnects have been deleted, leaving only the ground fill and ground traces, along with the vias between the front and back. Figure 8C is a simple stick diagram of the ground routing for the board. Each stick, or leg, represents the path of the ground conductor, as if the conductor has been shrunk down to a minimum-width trace. The top-side traces are represented by the dashed line, and the bottom-side traces by the solid line. It is easy to see in this diagram that most traces are dead ends.

Most traces are connected at only one end. In Figure 8D, most of the single-ended traces have been removed. The result is a sparsely connected pattern that represents how ground is routed over the entire board. Excluding points W, X, Y, and Z in Figure 8D, there is only one path between any two points anywhere on the routing. In Figures 8E, 8F, 8G, and 8H, the design has been modified very slightly, to achieve a gridded ground. In Figures 8E and 8F, the addition of some traces, shown in solid black, and slightly moving some geometries, as indicated by the arrows, has created an extensive network of interconnections that creates the desired grid. This is shown by the stick diagram of ground in Figure 8G. Closing the gaps around the mounting holes also contributes to the network. No longer are whole traces connected at only one end. Now, they connect at both ends, and form a more complete conductor. Figure 8H shows the density of the grid, which contrasts to the openness of Figure 8D. Also, notice how, in Figure 8H, no traces are dropped because they connect only at one end. Only one trace has this problem, and it is part of a geometry already connected in three other locations. This interconnected network is the goal of gridding ground. The result is nearly as effective as an actual ground plane.

2.2.4 Bypassing and Ferrite Beads
Bypassing between the +V and ground at the microcomputer is critical because the intent is for the capacitance to supply the current used in the device for switching. If the current is not available in the bypassing loop, because of too much inductance, the laws of physics say that the current should come to the lowest impedance, which then is from the leads connecting to the power supply. The distributed capacitance of the power routing becomes the source for the higher frequencies. Thus, the ferrite bead blocks the sourcing of RF current from the power line connection, forcing the microcomputer to live off the current available inside the ferrite bead.

It is of the utmost importance to realize, and always keep in mind, that the power-routing purpose is only to replenish the charge in the bypassing capacitor, and that the bypassing capacitor should supply all currents at or above the oscillator frequency. Keeping RF off the power distribution traces is accomplished using these measures (see Figure 9):
• Use a ferrite bead and a bypassing capacitor (0.1 mF or 0.01 mF), placing the capacitors inside the ferrite bead. Place a 1000-pF capacitor outside the ferrite bead, creating a PI filter. The ground connection for this capacitor should be the microground. However, if there is a lot of noise on this point, the capacitor could couple that noise back onto the +V line.
• The ferrite bead is used only on +V, not on ground. If a through-hole ferrite bead is used, it is mounted with the exposed lead connected to +V.
• Apply the 3:1 length-to-width rule for traces in the bypassing loop, to minimize impedance in this high-frequency path.
• Make the bypassing loops as small as possible in area and length. When tying the bypass capacitors for the oscillator or +V supply, try to extend the microcomputer ground rather than running a trace. Try to run any trace back over (or under) any other segment of the loop to reduce the radiating area when viewed from the top of the board.
• It is acceptable and beneficial to use ferrite beads and the same bypassing values on four-layer boards. The 1000-pF capacitor may not be needed on four-layer boards, but it should be drawn in the initial design, and deleted later if screen-room testing shows that it is not needed.



2.2.5 Keeping Noise Close to the Chip
The following applies to pins that are used for simple digital I/O, not for pins used in the memory-expansion bus. The goal here is not so much to reduce the noise of the edge switching, but to mute the noise of the clock glitches when the pin is static.

Noise on the pins is coupled internal to the device through many paths that can change as the pin function changes. For example, the input pin in a keyboard scan has capacitively coupled noise from both the substrate and the power rails. Also, because it is high impedance, any ambient fields couple efficiently. When the key is pushed, the pin has a new set of noise sources because the signal line’s impedance has changed. Thus, it is difficult to effectively develop a matrix of all possibilities; therefore, the
following is recommended:
• Put a 50 –100-W resistor in series with every output pin, and 35 – 50-W resistor on every input pin. If the system design calls for higher series resistance, use that value. Higher resistances are better for outputs, but usually do not improve characteristics of inputs. Place the resistor as close as possible to the microcomputer, overlapping the microcomputer ground if possible.
• Bypass any pin on the microcomputer to ground using a 1000-pF capacitor, provided the edge rate needed for the signal line is not faster than 100 ns. On outputs and pins that the system uses for both input and output, ground for the capacitor should be the microcomputer ground. The other end of the capacitor should be tied to the receiver side, not the microcomputer side, of the series resistor. Placing the capacitor inside the resistor makes the load seen by the microcomputer look like a short when it switches, which is not desirable. If adding the capacitor has to be traded off against placing the series resistor, because of space limitations, place only the resistor.
• On pins used for input only, place the capacitor inside, on the microcomputer side, of the resistor to reduce the loop area. Then, high frequencies originating in the microcomputer on the pin see less impedance to ground through the capacitor than through the resistor.
• Resets and interrupts are special functions, thus care must be taken not to reduce functionality.
• Do not apply any of the above remedies to oscillator pins. If proper spacing between the oscillator components and other unrelated components and traces is maintained, there should not be a need for oscillator signal conditioning.
• Unused pins should be configured as inputs and tied directly to the microcomputer ground. It is recommended that the watchdog be enabled to correct the unlikely event in which a device is disturbed, loses its program counter, and executes code to make the input become an output with a high level.

These rules take up space and add components, and so are not well accepted in production. The goal is to implement all rules on all I/O pins, but if that is not possible, then rank order the candidates least likely to cause noise and remove the application of these rules one pin at a time. Filtering priorities from most needed to least needed are:
• Signals leaving the enclosure (see section 3.3, Cables and Bypassing to the Shield)
• Signals leaving the PCB to other boards inside the enclosure
• Signals staying on the PCB with high-impedance loads (i.e., driving another MOS input or open circuit)
• Pins of parallel I/O port designed to support high-speed data transfer, e.g., between the microcomputer and an external memory, need filtering over the remaining I/O pins, because of their faster rise and fall times. When the design is complete and first prototypes are built, an hour or two in the screen room removing each of the filtering components one at a time, identifies which are or are not needed to get the desired EMI level.

2.3 Board Zoning
Board zoning has the same basic meaning as board floor planning, which is the process of defining the general location of components on the blank PCB before drawing in any traces. Board zoning goes a little bit further in that it includes the process of placing like functions on a board in the same general area, as opposed to mixing them together (see Figure 10). High-speed logic, including micros, are placed close to the power supply, with slower components located farther away, and analog components even farther still. With this arrangement, the high-speed logic has less chance to pollute other signal traces. It is especially important that oscillator tank loops be located away from analog circuits, low-speed signals, and connectors. This applies both to the board, and the space inside the box containing the board. Do not design in cable assemblies that fold over the oscillator or the microcomputer after final assembly, because they can pick up noise and carry it elsewhere. In prioritizing component placement, the most important things to do in PCB design are:
• Locate the microcomputer next to the voltage regulator, and the voltage regulator next to where VBatt enters the board.
• Built a gridded or solid ground between the three (forming a single-point ground), and tie the shield at that point.



2.4.1 Capacitive and Inductive Crosstalk
Capacitive and inductive crosstalk occur between traces that run parallel for even a short distance. In capacitive coupling, a rising edge on the source causes a rising edge on the victim. In inductive coupling, the voltage change on the victim is in the opposite direction as the changing edge on the source. Most instances of crosstalk are capacitive.

The amount of noise on the victim is proportional to the parallel distance, the frequency, the amplitude of the voltage swing on the source, and the impedance of the victim, and inversely proportional to the separation distance. Measures that reduce crosstalk are:
• Keeping RF-noise-carrying traces that are connected to the microcomputer away from other signals so they do not pick up noise.
• Signals that may become victims of noise should have their return ground run underneath them, which serves to reduce their impedance, thus reducing the noise voltage and any radiating area.
• Never run noisy traces on the outside edge of the board.
• If possible, group a number of noisy traces together surrounded by ground traces.
• Keep non-noisy traces away from areas on the board were they could pick up noise, such as connectors, oscillator circuits, relays, and relay drivers.
Most EMI-related crosstalk problems center around the crystal, when the victim is located too close. No unrelated components should be closer than 1 inch to the crystal.

2.4.2 Antenna Factor Length Rules
Normally, for Federal Communication Commission (FCC) limits, trace length becomes important when it is greater than 1/10 of the wavelength. For military standard limits, that number becomes 1/20 to 1/30 of the wavelength. For automotive and consumer two-layer boards, 1/50 of the wavelength begins to be critical, particularly in unshielded applications. That says traces longer than 4 inches can be a problem for FM-band noise. In these cases, some form of termination is recommended to prevent ringing.

2.4.3 Series Termination, Transmission Lines
The main purpose of termination is to provide critical damping to achieve the highest possible data transmission rates with the least-possible overshoot. When applied to most microcontroller systems, however, the focus changes to taking out as much total differential-mode noise as possible while allowing system functionality. Below is a table of different methods of termination and the main characteristics of each method.

Table 1. Termination Characteristics



Note that CMOS is an under-damped technology, which means that you always have to be on guard for ringing and overshoot. Use some form of termination if any of the following conditions are present:
• A signal trace is more than 1 foot long.
• A signal goes to a cable that leaves the shielded enclosure.
• Any ringing is present.
Series resistance is an inexpensive solution to termination and ringing problems, and is the preferred method for microcomputer-based systems where minimizing the differential-mode noise is also a concern.

2.4.4 Impedance Matching at Inputs
The input to a CMOS device looks like a series inductance of about 5 – 40 nH, which leads to about 5 pF in parallel, with about 5 MW to the grounded substrate (see Figure 11). This is a very high impedance, and can lead to lots of ringing and other noise if the device driving the input is not matched in some fashion to the higher impedance. This is the complement of the situation of section 2.4.3, where attention is paid to the microcomputer’s output because of the under-damped nature of the load it drives. Here, the microcomputer is the under-damped load, and ringing and overshoot are real possibilities. More than likely, some form of termination will be required, and again, the series resistance is the most likely solution. Resistance placed at the driver increases the output impedance, as seen by the trace and the input pin, thus matching the high impedance of the input.

If the input is connected to an open trace, such as the open line to a switch, a pullup or pulldown resistor is recommended. While this increases the amount of current switched when the input is activated, it reduces the impedance at all other times. This reduces the trace’s chances of being a victim of coupled noise.



2.5 Cables and Connectors
A well-designed two-layer board, and most four-layer boards, have minimal radiation. The problem at the system level is the radiation due to cables interconnecting the PCB with any off-board support function, other processor, or display and keypad PCBs. Because usually there is only one ground wire between boards, that one inductive wire has to return all of the RF energy carried onto the second PCB by the other wires. If there is any impedance in the single ground wire, a portion of the RF energy does not return to the microcomputer’s PCB via the ground wire, but rather through a radiated path. The energy radiates off the second board and couple back to the first, but, during the process, that radiation also can add noise in other locations in the system, as well as become direct radiation measured in the screen room. The key corrective action is to ensure the conducted path for the return has a very low RF impedance.

2.5.1 Differential-Mode and Common-Mode Noise
Common-mode noise is a big problem in cables, but the fault does not lie in the cable, it lies in the connections on the board that the signals and returns tie to that form the common impedance. Common-mode noise is corrected either at the source, by reducing the impedance of the common node, or reduced by placing a ferrite bead around the entire cable. Differential-mode noise (the useful noise of an edge transition) should first be reduced to the maximum (slowest) allowable rise and fall times and should occur at only the minimum needed frequency. The noise radiated is due to the loop of the signal and its return. This loop is minimized by having as many returns as possible and by twisting each signal and return pair. The latter causes field cancellation at some distance away, in the same manner as routing power over ground.

2.5.2 Crosstalk Model
Crosstalk in a cable is the same as in the PCB. Noise is coupled from the source onto quiet victim signals. Therefore, run clocking or other high-speed wires twisted with their own separate return. Crosstalk is a problem in cables over 2-meters long, and can be a problem in cables as short as 6 inches.

2.5.3 Number of Returns
It is common practice in the computer industry to have at least one ground for every nine other signal lines in a cable or harness. With higher speeds, this ratio is moving toward 1:5. These higher speeds are not limited to data rates, but also to harmonic content. Use these guidelines in designing signal and return lines:
• The best practice is to have one ground return for each signal in the cable, as a twisted pair.
• Never run less than one ground return for every nine signal lines, even if it is just the jumper cable to the front-panel display in a completely sealed metal box.
• If the cable is over one foot long, it should have one ground return line for four signal lines.
• When possible, there should be a solid metal bracket, used as a mechanical brace, soldered between the two boards, to serve as a mounting bracket and as a robust RF ground return.

2.5.4 I/O Recommendations for Off-PCB Signals
The PCB should have a large ground area tied to the enclosure shield that serves as the ground for the bypassing capacitors on each of the wires entering or leaving the enclosure. These capacitors provide final filtering of microcomputer noise, but also are intended to filter to the shield any noise picked up on the cable outside the box. See section 3.3, Cables and Bypassing to the Shield.

2.5.5 Keeping Noise and Electrostatic Discharge (ESD) Out
Noise and ESD incident on the cable are intended to pass through the bypass capacitor at the cable on the PCB and out to the shield (chassis). Therefore, the ground from the capacitor to shield should be wide (3:1) and bonded securely to the shield, preferably by two or more screws. The bypass capacitor value should be less than 1000 pF, so the effective series resistance (ESR) is minimum in the 50 – 500-MHz range. Lead length of axial devices would be a factor in the ESR, so surface-mount components are preferred.

2.6 Other Layout Issues
2.6.1 Front-Panel PCB with Keypad and Display in Automotive and Consumer Applications
In multi-PCB applications, a front-panel PCB, which carries the display and the keyboard, is part of the shielding enclosure. It also can be a source of emissions. The goal here is to make the ground return for the noise of the microcomputer, and to create an effective extension of the shield over the front of the box. This can be done by defining all lines on one side of the board to run one way, and the other side to run at 90 degrees (see Figure 12). Then, interspersed among the signals for keyboard and matrix, are the lines that make up two separate gridded ground planes: one that serves as the ground return and one that serves as part of the shield. The latter should securely contact the chassis at each corner and every two inches along the edge. The return ground plane should tie to the microcomputer’s ground plane, preferably using something heavy, like soldered-in metal braces. This prevents the impedance between the controller and the front-panel PCB from being a major problem.



2.6.2 Layout for Susceptibility
Susceptibility (called immunity in Europe) occurs as incident electric or magnetic fields couple onto signal traces. Because the coupled signal is alternating current, the sine wave is superimposed on voltage already present on the trace. At the input to a microcomputer, that voltage is rectified, and causes a dc offset voltage on the pin. When this dc voltage gets large enough to shift the input away from the switching-point voltage, the intended switching function is no longer seen by the microcomputer. If the input is the oscillator, the device suddenly has no clocks. If the input is reset, the device may go into reset and stay there until the disturbing field is removed.

The physics of susceptibility are the same as for emissions, only applied in reverse. Large loop areas pick up more signal, just as they would radiate more signal. Therefore, the things you do to keep a signal immune from radiation are the same as those to keep it from radiating. The most important pins for immunity are those that affect program control: the oscillator, reset, interrupts, and any input pins used for program branching. Apply the same rules as for reducing radiation from these pins. By far, most susceptibility problems are associated with the loop defined by the oscillator pins, the crystal, the crystal bypass capacitors, and the path between the bypass-capacitor ground connection and the ground of the microcomputer.

Also, be careful of ground bounce (common impedance coupling) of circuits that may generate these more critical signals. If the ground path has high impedance, it may cause the driving circuit’s reference voltage to shift, causing that input to the microcomputer (RESET, OSC) to be outside the switching range of the microcomputer.

2.6.3 Autorouters
Autorouters for PCBs do not take any noise reduction actions; therefore, care should be taken in their use. Power and ground routing, as well as signals that impact susceptibility, should be laid out by hand. Any signal with clocked data, such as low address bits in a memory expansion bus, should be next. Only signals with switching rates below 50 kHz can be left safely to the autorouter. Even then, every signal should be checked for EMI issues. Routing near the crystal, and the crystal and tank circuit itself, should be checked. Finally, the ground traces should be gridded.

3 Shielding
3.1 How It Works
When an incident electric field traveling in the air hits a metal surface, the metal causes the penetrating field strength to decrease. The metal causes the field to be replaced with conduction currents that flow in the metal close to the surface. A very small (exponential decay) amount of the field does pass through, but for emissions, this is never a problem. The metal chassis serves as a shield. The fields from all the radiating surfaces inside it are blocked and kept inside the box, with the only noise coming from the cables or wires that enter or exit the box and from holes or slots made in the box.

If a metal enclosure is to be used, its shielding effect should be utilized. However, it is always better to reduce the noise inside the box than to rely on the shielding effectiveness.

3.2 Grounding the Shield
The shield has the difficult job of providing a terminating or conducting surface for direct ESD hits, ambient fields, and internal fields, as well as noise carried on the cables entering and exiting the chassis. To do this well, the shield should be thought of as an RF conducting plane, with the least number of breaks and impedance’s between the source of the RF currents and the ground reference point. The ground reference point should be the single point, as mentioned earlier, that ties together the regulator ground, the microcomputer ground, and battery negative.

3.3 Cables and Bypassing to the Shield
The PCB should have a large separate ground area tied to the enclosure shield which serves as the ground for the I/O bypassing capacitors (see Figure 13). These capacitors provide final filtering of system noise, but also are intended to filter noise picked up on the cable outside the box. The value of the capacitor should be below 1000 pF, more likely about 470 pF. The connection to the chassis is an RF path requiring 3:1 length to width.


3.4 Slot Antennas: Cooling Slots and Seams
Slots antennas are formed by long thin gaps in the shielding material, such as at the seams between the two pieces of the box, and at the front-panel interface. These slots are very effective radiators. It is important that some form of contact assurance be used, such as dimpling, or using alternating fingers, to insure contact between the two surfaces. No slot should be more than 4 inches long. Cooling slots should not be used. For emissions reasons, only small round holes should be used if ventilation
is needed.

4 Summary
The design of systems that generate low electromagnetic interference is not a mystery, but requires application of well-known engineering techniques. The design begins with the selection of semiconductor components that produce low electromagnetic radiation. However, in many cases, other criteria, such as the required performance of the semiconductor component, may be in contradiction with low interference. The main task is the design of a PCB that eliminates antennas that can radiate electromagnetic energy. Even if this can be achieved sometimes, large loops of signal and corresponding ground-return lines that carry high frequencies must be avoided. Therefore, a careful positioning of the integrated circuits is essential to achieve short interconnect lines.

In the next step, a close ground grid is placed over the printed circuit board. This grid ensures that return lines are close to the signal lines, thus keeping the effective antenna area small. A ground plane in a multilayer board provides this feature. By using this technique, low electromagnetic emission can be achieved with low design effort. However, some cost-sensitive applications allow two-layer PCBs only. Nevertheless, in this case, careful layout provides nearly the same performance as a multilayer board.

Finally, filtering of critical lines, such as the supply line, ensures that high-frequency currents do not leave the PCB. By applying the rules presented in this report, shielding of the total system is not required. Experience and careful work by the design engineer are much more effective than sophisticated computer-aided design tools.

5, PCB design Tools

Printed circuit boards (PCBs) are created by layering insulating material and electrical conductors. The circuit boards are either single or multiple sided. PCB design tools allow designers to create the layouts for these boards. While there are some free PCB design software programs, most of these programs require a fee to use.

FreePCB
FreePCB is an open-source program, which means that a community of designers work on these projects. FreePCB is compatible with Microsoft Windows. The program operates under the GNU General Public License, which means that users can share and manipulate the program as they see fit. The target audience for this software program is beginners, but it does have some advanced features that professionals can use. Users can create boards with up to 16 copper layers and boards up to 60x60 inches. The system features autosave, which automatically saves a user's work as he is working. The program also comes with both a Footprint Wizard and Footprint Editor. This way, users can quickly create and edit footprints (data for component parts). The system comes with a user guide to help new users.

ExpressPCB
The target audience for ExpressPCB is new designers. The program is free to use the design software, but users must pay for the circuit boards if they decide to manufacture them. Users can design either a two- or four-layer board. ExpressPCB uses a drop-and-drag design interface, which allows users to drop in component footprints; users simply drag them into place. Individual components (pins) are connected using a drawing tool. The program can also point out pins that should be connected, which will show up in blue. The system uses a graphical user interface (GUI) to allow beginners to create designs without ever having to write code.

EAGLE Version 5.10
The EAGLE tool is compatible with the three major operating systems: Linux, Mac and Windows. While users must buy the full version, a freeware version is available that allows users to create simple designs for free. The system uses a graphical user interface and a PCB wizard. When a user starts a new project, a window will open up with an outline based on the default settings. This tool uses a drag-and-drop feature to pick up and move components to their correct location. Users can also select and move multiple components. Users have the choice to route their own signals (lines between components) using the Route command, or they can let the software do it via the Autorouter command.

6,PCB design experience

General basic PCB design flow as follows: preparation -> PCB design -> PCB Layout - > Cabling - > routing optimization and silk - > Network and DRC checks and structural inspection - > plate.

First: preparation. This includes preparing the library and schematics. " We must first sharpen his tools " to make a good board, in addition to good design principles , should also paint it . Before PCB design , the first to be ready SCH schematic and PCB library component library . Library can be used peotel own library, but under normal circumstances it is difficult to find a suitable , preferably their own standard size based on the information of the selected device's own component libraries. In principle, the PCB component libraries do first , do SCH component library . Higher PCB component library requirements, which directly affects the board installed ; SCH component library requires relatively loose , just pay attention to the definition of a good correspondence between the pin and the PCB component properties on the line . PS: Note that the standard library hidden pins. After that schematic design , ready to start doing well after the PCB design .

Second : PCB design . This step has been determined according to the size of the circuit board and the mechanical positioning , draw PCB board in the PCB design environment , and then positioning requirements connectors, buttons / switches, screw holes , place the required mounting holes so . And to fully consider and determine the routing area and the non- routing area ( eg screw holes around the extent to belong to the non- routing area ) .

Third : PCB layout. Layout that white is on the board to put the device . Then if mentioned earlier preparations are good , then you can generate a netlist (Design-> Create Netlist) on the schematic , and then import the netlist (Design-> Load Nets) on the PCB. I saw the device crashed whole heap up, as well as fly line connection between the pin tips . Then you can pair the device layout . The general layout of the following principles:

①. By electrical performance and reasonable zoning, generally divided into : digital circuit area ( ie fear of interference, and interference ) , analog circuit region ( fear of interference ) , power driver area ( sources of interference ) ;

②. Perform the same function in the circuit should be placed as close as possible , and adjust the various components to ensure the connection of the most concise ; while adjusting the relative position of each functional block to make the connection between the functional blocks among the most concise ;

③. For large mass components should consider the installation location and mounting strength ; heating element should be placed separately from the temperature-sensitive components, thermal convection measures should also be considered , if necessary ;

④. I / O -driven device as close to the edge of the printing plate , close to the lead connector ;

⑤. Clock generator ( eg : Crystal or Zhong ) to try to close the device clock used ;

⑥. Between each IC power input pin and ground , need to add a decoupling capacitor ( typically a good high-frequency performance monolithic capacitors ) ; dense when board space , but also add a few integrated circuits around tantalum capacitors.

⑦. To add a relay coil at discharge diode (1N4148 can ) ;

⑧. Layout requirements should be balanced , density and orderly , not top-heavy or a sink

- Require special attention when placing components , be sure to consider the actual size of the ( occupied area and height ) components , the relative position between components , in order to ensure the feasibility of the electrical properties of the circuit board and production installation and convenience at the same time , it should be able to reflect the principle of ensuring the above premise , the proper place to modify the device to make it neat appearance, such as the same device to be placed neatly in the same direction , you can not put too " patchwork ."

This step is related to the degree of difficulty and the overall image of the next wiring board , so it takes a great effort to consider. When the layout , not sure where to preliminary wiring can be fully considered.

Fourth: cabling. PCB design layout is the most important step . This will directly affect the quality of the performance of the PCB . In the PCB design process , so the wiring are generally divided into three phases : the first is through the cloth , the basic requirement of PCB design time . If the line did not pass the cloth , and made full fly line , it would be a failure of the board, it can be said yet started. Followed by the electrical performance of the meet . It is a measure of a printed circuit board eligibility criteria. This was after Bouton , carefully adjust the wiring so that it can achieve the best electrical performance. Next is beautiful. If your wiring through the cloth , there is no impact on electrical performance places, but a glance disorganized , plus colorful, colorful , and that even if you how good electrical properties , in the eyes of others or refuse a . To test and repair this great inconvenience . Wiring to uniform, not criss-cross clueless . These should be in ensuring the electrical performance and meet other requirements of the individual case to achieve , otherwise the forest for the trees . The main wiring according to the following principles:

①. Under normal circumstances, the first response to power and ground wiring to ensure that the electrical performance of the circuit board. In the conditions permit, try to widen the power , ground width , preferably ground than the power line width, their relationship is : Ground > Power cable> signal line , usually signal line width : 0.2 ~ 0.3mm , the smallest width of up to 0.05 ~ 0.07mm, the power cord is generally 1.2 ~ 2.5mm. Available on a wide PCB ground wire digital circuits to form a loop , constitutes a ground network to use ( analog circuit ground so you can not use )

②. More stringent requirements in advance of the line ( such as high-frequency cable ) wiring , input and output terminals of adjacent parallel edges should be avoided to avoid reflection interference. Necessary, add ground isolation , wiring two adjacent layers perpendicular to each other and parallel prone to parasitic coupling.

②. More stringent requirements in advance of the line ( such as high-frequency cable ) wiring , input and output terminals of adjacent parallel edges should be avoided to avoid reflection interference. Necessary, add ground isolation , wiring two adjacent layers perpendicular to each other and parallel prone to parasitic coupling.

③. Oscillator shell ground , the clock line as short as possible , and can not be attracted everywhere. Clock oscillation circuit below , a special high-speed logic circuit part to increase the land area , and should not take the other signal lines to the surrounding farms close to zero ;

④. As far as possible 45o polyline wiring , do not use a line 90o to reduce high-frequency signal radiation ; ( lines also require high double arc )

⑤. Do not any signal line to form a loop , as is inevitable , the loop should be as small as possible ; vias to minimize signal line ;

⑥. The key lines as short and thick, and on both sides of a protective ground.

⑦. When sending sensitive signal and noise signal through the field with a flat cable , use the "ground - signal - ground " approach leads.

⑧. The key signal test points should be set aside to facilitate the production and maintenance of detection

⑨. After completion of wiring schematics , wiring respond optimized ; Meanwhile , after a preliminary examination and DRC network after checking correct wiring area on the ground is not filled with a large area for the ground layer of copper on the PCB is not spend the places connected with the land use as a ground . Or made ​​of plywood , power , occupied the ground floor of each .

- PCB layout process requirements

①. Line

In general, the signal line width is 0.3mm (12mil), the power supply line width 0.77mm (30mil) or 1.27mm (50mil); distance between lines and between the lines and the pad is not less than 0.33mm (13mil ) , practical application , conditions permitting, should be considered to increase the distance ;

At higher wiring density can be considered ( but not recommended ) using IC foot walk between two lines , the line width of 0.254mm (10mil), line spacing is not less than 0.254mm (10mil). Under special circumstances, when the device pins dense , narrow width , the line may be appropriate to reduce the line width and spacing .

②. Pad (PAD)

Pad (PAD) and the transition pore (VIA) The basic requirements are: disc diameter than the diameter of the hole is larger than 0.6mm; For example , GM pins resistors , capacitors and integrated circuits , the use of disk / Hole Size 1.6mm/0.8 mm (63mil/32mil), sockets, pins and diodes 1N4007 , etc., using 1.8mm/1.0mm (71mil/39mil). Practical application, should be based on the size of the actual components to be, when conditions may be appropriate to increase the pad size ;

PCB board design element mounting aperture should be larger than the actual size of the component pin is about 0.2 ~ 0.4mm.

③. Vias (VIA)

Generally 1.27mm/0.7mm (50mil/28mil);

When high wiring density , vias may be appropriate to reduce the size , but not too small , consider using 1.0mm/0.6mm (40mil/24mil).

④. Spacing pad lines , vias request

PAD and VIA: ≥ 0.3mm (12mil)

PAD and PAD: ≥ 0.3mm (12mil)

PAD and TRACK: ≥ 0.3mm (12mil)

TRACK and TRACK: ≥ 0.3mm (12mil)

Higher density :

PAD and VIA: ≥ 0.254mm (10mil)

PAD and PAD: ≥ 0.254mm (10mil)

PAD and TRACK: ≥ 0.254mm (10mil)

TRACK and TRACK: ≥ 0.254mm (10mil)

Fifth : wiring optimization and printing . "There is no best , only better !" No matter how you rack their brains to design, etc. After you finish the painting , go take a look , still feel a lot of places that can be modified . Experience in general design are: optimizing routing time is twice the initial wiring time . I feel no need to modify the following places , you can shop the copper (Place-> polygon Plane). General Shop Shop copper ground wire ( Note that the analog and digital ground separation ) , plywood may also involve laying off. When the screen , be careful not to be blocked by the device or vias and pads removed. Meanwhile, the design element face to face , mirroring the underlying word processing should be done to avoid confusion levels.

Sixth : Network and DRC checks and structural inspection . First, in determining circuit schematic design premise is correct , the generated PCB schematics network file and check the physical network connection for network file relationships (NETCHECK), and timely correction of design based on the results of the output file to ensure that wiring connection correctness relations ;

After checking the correct network through , for PCB design DRC, and timely correction of design based on the results of the output file to ensure that the performance of PCB electrical wiring . Finally, the mechanical mounting structure for further inspection and confirmation of the PCB .

Seventh : plate. Prior to this, there is also preferably an audit process.

PCB design is a work of reference mind , who thought dense, high experience, designed like a board . So be extremely careful design , fully consider all aspects of the factors ( for example, ease of maintenance and inspection which a lot of people do not go to be considered ) , excellence , we will be able to design a good board .

7, PCB Design Basic

This article discusses the major steps in the PCB design flow, from basic terminology to the primary steps required to move an example design through the schematic, layout, and manufacturing stages.

Understanding the Terminology
Schematic capture and simulation tools – A schematic capture program allows the user to draw a document representing the electrical component symbols and the interconnections between them in a graphical way. Before generating a PCB, the symbols are mapped to component footprints and the symbol interconnections are converted to a netlist that specifies the connections between the component footprints in the layout process. A schematic tool that allows the user to do interactive circuit simulation with the same schematic circuit representation used for layout is advantageous. Circuit simulation can be useful for both initial design analysis and testing the design (i.e. verification testing and troubleshooting) once complete.

PCB layout tools – A PCB layout program generates the mechanical and wiring connection structure of the PCB from the netlist. The layout program allows the wiring connection structure to be placed on multiple layers and, once complete, allows the user to generate the computer aided design (CAD) files needed to manufacture a PCB.

Gerber files – The CAD files that need to be sent to a PCB manufacturer so it can build the PCB layer structure are called Gerber files. The RS-274X is the most commonly supported Gerber file format.

NC drill files – The numerically controlled (NC) drill files indicate the size and position of holes used for unplated holes, plated through-holes, or holes for vias. Some quick-turn PCB manufacturers have only select hole sizes available.

Printed circuit board (PCB) – A wafer board defining the mechanical and copper wire structure of the circuit. (It is sometimes called a PWB for printed wiring board).

PCB structure and details
A PCB can be considered a layered structure, usually with multiple copper and insulating layers. The main portion is a non-conductive (insulative) material (substrate) usually made from fiber glass, and epoxy. The substrate material used to separate layers comes in different thicknesses, from 0.005” to 0.038”. Conducting layers consist of copper (Cu) foils that are etched away in specific areas where the user does NOT want connections to occur. A single-layer PCB has the substrate with one layer of copper foil on the top (see Figure 1).


A double layer PCB (see Figure 2) has two layers of copper foil (one on the top and one on the bottom).

Home> PCB Design Center > How To Article
PCB design basics
Mahmoud Wahby - November 13, 2013
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PRINT PDF EMAIL This is the first of several articles in the PCB Design Best Practices series, which discusses the different steps of PCB development from the basics of creating a design schematic with specific requirements, to finalizing a board and preparing it for fabrication. The articles will use examples from National Instruments circuit design tools NI Multisim and NI Ultiboard.

This article discusses the major steps in the PCB design flow, from basic terminology to the primary steps required to move an example design through the schematic, layout, and manufacturing stages.

Understanding the Terminology
Schematic capture and simulation tools – A schematic capture program allows the user to draw a document representing the electrical component symbols and the interconnections between them in a graphical way. Before generating a PCB, the symbols are mapped to component footprints and the symbol interconnections are converted to a netlist that specifies the connections between the component footprints in the layout process. A schematic tool that allows the user to do interactive circuit simulation with the same schematic circuit representation used for layout is advantageous. Circuit simulation can be useful for both initial design analysis and testing the design (i.e. verification testing and troubleshooting) once complete.

PCB layout tools – A PCB layout program generates the mechanical and wiring connection structure of the PCB from the netlist. The layout program allows the wiring connection structure to be placed on multiple layers and, once complete, allows the user to generate the computer aided design (CAD) files needed to manufacture a PCB.

Gerber files – The CAD files that need to be sent to a PCB manufacturer so it can build the PCB layer structure are called Gerber files. The RS-274X is the most commonly supported Gerber file format.

NC drill files – The numerically controlled (NC) drill files indicate the size and position of holes used for unplated holes, plated through-holes, or holes for vias. Some quick-turn PCB manufacturers have only select hole sizes available.

printed circuit board (PCB) – A wafer board defining the mechanical and copper wire structure of the circuit. (It is sometimes called a PWB for printed wiring board).

PCB structure and details
A PCB can be considered a layered structure, usually with multiple copper and insulating layers. The main portion is a non-conductive (insulative) material (substrate) usually made from fiber glass, and epoxy. The substrate material used to separate layers comes in different thicknesses, from 0.005” to 0.038”. Conducting layers consist of copper (Cu) foils that are etched away in specific areas where the user does NOT want connections to occur. A single-layer PCB has the substrate with one layer of copper foil on the top (see Figure 1).

PCB Design Basics
Figure 1: Single layer PCB


A double layer PCB (see Figure 2) has two layers of copper foil (one on the top and one on the bottom).

PCB Design Basics


Figure 2: A double-layer PCB


If more than two layers are required due to increased complexity of the PCB, other layers of copper can be built-up or added to the ones shown above (usually in pairs). For example, a 4-layer PCB can be made up of two double-layered PCBs laminated (sandwiched) together with a core material in between. Made out of epoxy/fiber, this core layer is called a prepreg (pre-impregnated), and it insulates and supports the other layer structures. It is common for modestly complex boards to have 6, 8, or 10 layers (with increased manufacturing cost). Some highly complex PCBs have up to 32 layers or more of traces and copper planes (see Figure 3).

PCB Design Basics
The height of the substrate is usually the thickness of one or multiple sheets of laminate material and is usually much smaller than the height of the core prepreg material layer.

Multilayer PCB – A PCB with more than one copper foil layer. The layers are preferably renamed in the design tool to unique names (such as power or ground) as desired by the user.

Layer Stack Up – The copper organization of multiple layer PCBs with the intent of having specific signal and ground planes on certain layers for routing convenience and electromagnetic shielding purpose. A four-layer board will typically have the following layer structure, where the top and bottom layers are reserved for signal routing and the inner layers are reserved for ground and power planes:

• Copper Top
• Inner 1
• Inner 2
• Copper Bottom


Finished PCB Height - Standard finished PCB thicknesses are commonly found as shown – this thickness includes all copper, substrate and prepeg layers:

• .031” (also .039" is common)
• .062" (most commonly used size)
• .093"
• .125"


Shown in Figure 4 is a more realistic layer stackup of a four-layer PCB showing the various thicknesses of the layer structures from a typical PCB manufacturer yielding the common 0.062” finished PCB height.

PCB Design Basics

8,PCB design basic idea

1), the concept of "Layer (Layer)"

With word processing or many other software for the realization of the image, text, color and other nested and synthesis and introducing the concept of "layer" with somewhat, Protel "layer" is not virtual, truly, truly, but the printing plate material itself of the copper foil layer. Nowadays, because of the electronic circuit element intensive installation. Anti interference and wiring and other special requirements, some of the newer electronic products used in the printing plate have upside down for walk the line, not only in the middle of the plate can be also has special processing mezzanine copper foil, for example, now computer motherboard used much in more than 4 layer board materials.Most of these layer due to the machining is relatively difficult to walk line relatively simple Power wiring layer (such as Ground in software Dever and Power Dever), and the commonly used large filling way to wiring (such as in software ExternaI P1a11e and the Fill). And the location of the surface layer and the place of intermediate layers need to be connected with the software mentioned in the so-called "hole (Via)" to communicate. With the above explanation, it is not hard to understand "multi-layer welding plate" and "wiring layer Settings" on the concept. A simple example, many people wiring is complete, to print it out when they found a lot of connection terminal bonding pad, it is his own add components library ignores the concept of "Layer", did not draw his encapsulation of bonding pad feature is defined as "multi-layer (Mulii Layer). To remind is, once selected the Layer number of the board is used, be sure to shut down those unused layers, avoiding detours.

2), Via (Via)

For connecting line between each layer, each layer needs to be connected the wires wenhui place a public hole drilling, this is a hole. Process in a hole on the wall of hole on cylinder with a layer of metal plating, chemical deposition method is used to connect the copper foil of intermediate layers need to be connected, and via both sides make ordinary welding plate shape, can be directly with upper and lower sides of the line, also is not even. In general, when designing circuit right hole processing has the following principles:

(1) Holes use less as far as possible, if chose a hole, it is important to deal with it and the surrounding each entity's clearance, especially easy to ignore in the middle of each layer and a hole is not connected to the line and hole clearance, if it is a automatic wiring, can be in "number Via minimization" (Via Minimiz8tion) in the sub menu select "on" to automatically resolve.

(2) the carrying capacity, the greater the need for a hole size is larger, such as power supply layer and layer formation with other join the hole will be larger.

3)、Overlay(Overlay)

For the convenience of installation and maintenance of the circuit, etc., in the printing plate need logo on the upper and lower surface of the printing design and writing code and so on, such as component label and nominal value, components outside the profile shape and the signs of the manufacturer, production date, etc. Many beginners the contents of the silk screen layer, only pay attention to the text symbols placed in neatly beautiful, ignoring the actual effect of PCB making. They design on the board of character is not is blocked by element is invaded help welding area has been put on credit, and the components of label on the adjacent components, so the design will bring great inconvenience to assembly and maintenance. Correct printing layer character layout principle is: "don't ambiguity, and the beauty is generous."

4), the particularity of SMD

There are a lot of SMD encapsulation, Protel encapsulation of the rolls surface welding device. The biggest characteristic of this kind of device in addition to small size is single distribution yuan pin hole. Therefore, choose this kind of device to define a good device in the face, in order to avoid "Missing pin (Missing Plns)". In addition, this kind of components related to text annotation can only with the component's presence.

5), grid filling area (External Plane) and populate the area (Fill)

Network as their name suggests, the fill area is the copper foil processing into a network of large area, populated area is only intact copper foil. On the computer in the process of beginners tend to see the difference between the two, in essence, as long as you to enlarge drawings after the be clear at a glance. It is usually not easy to tell the difference, so when using less attention to the distinction between the two, want to stress is that the former has the strong according to the characteristic of the circuit to inhibit the action of the high frequency interference, is suitable for large area filling should be done in place, especially in the areas as shielding area, divided area or high current is particularly appropriate when the power cord. The latter is more used for general wire ends or turning area need to fill small area, etc.

6), welding plate (Pad)

Welding plate is PCB design "> most often contacts in the PCB design is also the most important concept, but beginners tend to ignore it and correction, the choice of using circular pad in the design of the same. Select element type of bonding pad to comprehensively consider the elements of shape, size, layout, vibration and heat conditions, factors such as stress direction. Protel in encapsulation repository is given a series of different size and shape of the solder, such as round, square, octagon, round square and positioning with solder, etc., but sometimes it is not enough to use, the need to edit. For example, the fever and stress is larger, the current large welding plate, can be designed into tears" shape ", in the familiar PCB line output transformer of TV in the design of the pin pad, many manufacturers is adopted in this form. In general, when editorial solder in addition to the above said, consider the following principles:

(1) shape length doesn't conform to consider connection width and the size of the weld length of side plate of a particular difference too much;

(2) need to choose when walk line length between components lead Angle asymmetry of bonding pad often get twice the result with half the effort;

(3) all the components according to the size of the welding plate hole components pin thickness editor determined respectively, the principle is the size of the hole is bigger than the pin diameter 0.2 0.4 mm.

7), all kinds of membrane (Mask)

The membranes not only is necessary, in the process of PcB production process and components necessary for welding. According to the position of "membrane" and its role, "membrane" can be divided into components or welding surface run-off membrane (TOp or Bottom and the surface of the element (or welding surface) resistance welding membrane (TOp or BottomPaste Mask) two kinds. As the name implies, run-off film is coated on the bonding pad, to improve the performance of weldable a membrane, which is in the green board is slightly superior to pad the light round spot. Resistance welding film is just the opposite, in order to adapt the board made of wave soldering welding such as form, requirements on board, a plate of copper foil can't stick tin, so outside welding plate parts are coated with a layer of paint, used to prevent these parts on the tin. Visible, these two kinds of membrane is a complementary relationship. This discussion, it is not hard to determine the menu similar to the solder Mask En1argement "projects such as set up.

8), Line fly, fly line has a double meaning:

Automatic wiring like a rubber band for observation network connection, in the table to components through the network and makes a preliminary layout, with the "Show commands can see the layout of the network connection cross condition, position of constantly adjust components make the cross at least, to achieve maximum automatic wiring completion rate. This step is very important, can be said to be a knife and cutting wood work, spend more time and value. In addition, the automatic wiring end, what the network has not yet been cloth, also can through the function to find the. Find out cloth after pass network, manual compensation are available, and can't compensate the will use the second meaning of" fly line ", is in the future with wire connected on the board of the network. To hand over to treat, if the circuit board is large quantities of automatic line production, the fly line can be regarded as zero resistance, a unified welding plate spacing of the resistance element for design.

9, PCB Design

How to create SMD based PCBs
This tutorial will take you through a more advanced SMD layout. Its a marathon so get yourself a glass of wine and a mouse with a scroll wheel then dive in.

Were going to assume youve already read our other tutorials on through-hole PCB layout so you should already have Eagle and the various support files installed. We use keyboard shortcuts liberally so you better have them installed as well.

Lets create a tool that everyone should have in their toolbox: a USB to serial converter board. The FT230X is a pretty neat USB to serial converter that should do the job nicely for us.

Were going to assume youre using our library that contains the FT230X. If you want to learn how to create SMD footprints for Eagle from scratch, please see this tutorial.

Creating the Schematic

To start, create a new project in Eagle. Right click on the Projects folder and select New Project.

Call the project FT230X Breakout. Right click on the folder and select New Schematic.

Lets start by adding a frame to our schematic. From the Eagle main window, navigate to the Libraries folder. Click on the small arrow beside the word Libraries to expand it. Then expand the SparkFun-Aesthetics library (since the frame is just for aesthetics). Navigate to the FRAME LETTER component and click Add.

Drop the corner of the frame on the corner of the schematic layout window. Hit escape twice to return to the main schematic window.

Use the scroll wheel to zoom in/out. Press and hold the scroll wheel to drag the schematic window around.

Now lets add the various bits well need for this example:

FT230X component from the DigitalICs library. The best way to get to find the component is to click on any component then press f to take you to the components that start with f. Add this to your schematic. Click once to drop the item. Hit escape twice to return to Eagle main window.
M07 from the Connectors library. You will want the M07 device. This is the most common, 7 pin 0.1 header footprint.
USB from the Connectors library. You will want the USBSMD device (it has the USB-miniB package type).
5V, 3.3V, and GND from the Aesthetics library.
Two LEDs from the LED library. You will want LED0603. This is the small 0603 sized surface mount LED.
Two CAPs from Passives library. Get the CAP0603-CAP package.
CAP_POL from Passives library. Get the CAP_POL1206-KIT package.
Two Resistors from the Passives library. You will want RESISTOR0603-RES.
PTC from the PowerIC library. Get the PTCSMD package.
Four Stand-offs from Electromechanical. Get the STAND-OFF package.

Weve got all the parts here. Now hit F7 to go into move mode. Click on an item and move it around. Were aiming for the example found in the datasheet. Arrange your components kind of like this:

While you got a component selected and moving, rotate it by right-clicking. Left clicking will set the component down.

Now press F9 to begin wiring the components together. Click on the end of the D- pin on the USB connector and run it over to the USBDM pin on the FT230X. Click again on the pin and the wire should stop routing indicating that it has been successfully connected.

Continue to wire as shown.

You may get a window that says Merge net segment N$4 into supply net 5Vor some such warning. The answer is yes you do.

We will need more GND connections. Press F8 to go into copy mode. Click on the GND symbol and create 8 or so copies.

A trick I use a lot is this: Hit F7 to move the GND symbol. Move it directly onto the end of the capacitor and click to drop it.

Now click the same ground symbol and move it down. Eagle will automatically have a wire attached. This saves you from having to do a few wire connections by hand.

Wire up more stuff. Note the two stubs of wire on pins 5 and 6 on the 7 pin connector. Those are unnamed, unconnected nets.

Press Alt+F9 to go into Label mode. Then left-click on one stub. Eagle will highlight the wiring - this is its way of asking if that is the wire you want to be messing with.

Left click again to confirm - Eagle will then show a label for the stub. Click again to anchor the label to the stub. Repeat for the 2nd stub.

Now press F4 to go into Name mode. Click on the first stub. Are you sure you want to connect them? Yes you are. Repeat but name the second net 5V.

Press F5 to go into Value mode. Then click on R1 and set the value to 330. Set the values for the following:

R2 = 330
C1 = 0.1uF
C2 = 0.1uF
C3 = 10uF

Hey! Its about time you saved your work! Hit Ctrl+s or the disk icon. Save your work as FT230X-Breakout-v10. This is the first version so its v1.0. If there are changes to be made, save the file as -v11, -v12, etc.

Have a look. The values are sort of running over the wires. Lets press Alt+F7 to go into Group mode.

Move the cursor to the upper left corner. Click and hold the button down, then drag to the lower right corner. Note that we are selecting just past C2.

Release the mouse button. You should see a bunch of wires and components selected. Now weve got a group, but we havent told Eagle what we are doing with this group. Press F7 to go into Move mode. Now lets move the group! Holding Ctl, click the right mouse button. The group will now be moving with the mouse cursor.

Move it two clicks to the left so that the 0.1uF text doesnt overrun the GND symbol.

Lets create labels and name the nets near the connector. This will help us in the PCB layout phase. Press Alt+F9 to go into label mode. Click on a wire, Eagle will highlight it. Click again to confirm you want to mess with the highlighted wire. And click a third time to throw a label in that location. Once you have four random labels (such as N$9, N$13, etc), then hit F4 and rename the wires as shown in the picture:

TXO
RXI
RTS
CTS
Note the leading ! will put a line above the net name (neat!).

Looking pretty good! Lets start laying down traces.

Laying out the PCB


Now lets click on the Board button and start PCB layout!

Yes please create from schematic.

Whoa! Neat! Use the mouse wheel to zoom in and out. Click the mouse wheel and move the mouse to navigate around an area.

Now press F7 to go into move mode. Begin to move the parts to the lower corner of the PCB.

As youre moving stuff around, right click to rotate a part.

Youll see the rats nest of airwires update as you go. Be looking to rotate or position a component to try to minimize the overlap of wires. You wont get it all straightened out but this is the time to be thinking about it. Decent placement at this stage will make routing much easier later on. Regularly press F8 to update the rats nest.

We are getting there.

We now need to reduce the board shape to fit our rough arrangement of parts. You should see a thin white wire that makes a big square. This wire is on the dimension layer and represents your outer board shape. Press F7 then click on the white wire and move the sides of the board inward, making a tight box around your components.

Note: The USB connector can hang slightly over the edge.

Also, see the board outline near the cursor is not on grid? Press F7 to go into move mode. Then hold Ctrl while clicking on the corner of the dimension line.

The wire or component (whatever youre near) will jump onto the grid. This is a valuable trick to get stuff back on grid. Repeat with the upper right corner and lower left corner.

Ok - weve got everything packed in together pretty well. Take note of a couple things:

Draw a horizontal line across the middle of the board. Youll notice Ive located a lot of the components along the midline. This helps with aesthetics more than anything but also helps with some routing.

Do not attempt to pack everything in right next to each other. You will eventually be soldering these parts to the board and will need some room to get the iron and solder wick in there.
Lets take a moment to turn on ALL the layers to see if there are any problems.

Click on display, then the All button, then Ok.

Weve got a couple problems. Theres some text we didnt even know about (the creative commons license! Yay!). And you also see red rings around the stand-offs. These rings are on the top keepout layer. They are there to show the radius of the head of a standard screw. If we tried to put a screw into the breakout board it would hit the USB connector! Better spread things out.

Use the scroll wheel to zoom out. Hit F7 to grab and move the license below your board.

Remember to use the Alt+F7 group command to group stuff together, then press F7 to go into move mode, then Ctrl+right click to move the group. I used this trick to grab two standoff holes and the frame at the same time and made the board wider. Then grab more bits and bumped them up a few clicks.

Now press F11 to return all the layers to their original / default viewing state. This allows us to concentrate on layout. Lets start routing! Were going to route this board by hand to show more advanced routing techniques. You are welcome to use the auto-router if you please.

At SparkFun we route everything by hand. Yes everything. This is a change from my views a few years ago. We used to auto-route everything. The boards worked, but they looked awful. We like to think we should be pushing for a board that not only works but also looks good. Did I mention routing a board is like solving a puzzle? And I love puzzles!

Here is a quick breakdown of the key commands well be using:

Press F9 to lay a trace

Alt F9 to rip up one

Click on the middle of pad VBUS. Drag out the wire to a grid intersection (itll snap to it). Click again to anchor the trace, then click again to stop routing that trace.

Now start routing from the PTC. Click on the 1 pad. Drag trace out to intersection and down to other trace. You may hear a pleasant ding letting you know the trace is completed.

Continue the route after the PTC. Note that it goes down to the right side of the FT230X. Im worried about boxing out other traces so Ill just leave a stub of the trace here by double clicking.

The GND airwires are distracting me. Click on the i and then a GND wire. See the box at the bottom that says Airwires Hidden? Check that box and click ok. This will make all the ground airwires disappear. Well get the GND wires with a polygon pour later on.

Start attacking the easiest routes. Leave stubs where you see cross-over problems. See how far you can get without using a via. Well talk about those next!

Creating Vias

Now lets talk vias. Vias are a hole in the PCB that has metal running down the inside of the hole so that the traces on the front of the board are electrically connected via the hole to the back of the board.

Press F9 to go into routing mode and look for the Drill box in upper right corner. The default via size in Eagle is 0.02362205 (or more sanely 0.6mm). I change this to 0.02 (or 0.5mm if you please) and press enter to make Eagle save that size.

There is nothing magical about 0.02". This is a size that weve found most PCB fab houses can drill without too many tolerance issues. Its also small enough to tent over with soldermask making the board look a little better.

Press F9 to route from a pad. While youre routing hold the shift key while you left click. This will drop a via and youll continue to route on the top layer. Now click the middle mouse wheel. This will drop you to the bottom layer and you can keep routing.

Continue to route some of the other nets.

The above routing will work, but if we bump the highlighted via downward, we can straight out the blue trace a bit. Like this:

Nitpicking? A, bsolutely. But bumping various routes around can make the overall routing a lot cleaner over time.

Note that I keep nearly everything onto the 0.05 grid. This keeps routing and spacing a lot easier. The size (0.05) is reasonably trivial. The important piece is that all the components and general routing are kept on the same gr, id, .

Weve got two problems here. Two wires could be routed without vias if we ripped up the 8 to 9 route. The two wires also cross over themselves. Re-arranging the LEDs will fix this.

Fixed. However you may note the trace connecting Pin 11 on the FT230 is off grid. While routing, hold the Alt key to jump off grid. Going off grid is perfectly fine but as a rule of thumb, I try to keep on the grid as much as possible.

Removing the 8 to 9 route also opened it up so that we could route the D+ and D- traces directly to the IC.

Ah! Neat. If we move some stuff around, we can get !CTS routed without needing a via.

Theres obviously a DRC error here but we can fix it when need be. Lets just leave it in case other things change.

Now I need to get pin 8 connected to pin 1, but Eagle wont let me start routing from the lower via - it keeps wanting me to route from pin 8. To get around this, I am going to rip up some of the traces near the via so that I can have a starting point. Press Alt+F9 then click on a trace to rip it up.

I ripped up a small trace which gave me an airwire that I started routing from.

Re-routed. Note I still have a very small airwire that I need to route. Not hard, press F9, click on the airwire, click again, and itll route.

Polygon Pours

Looks pretty good. Now we need to get GND routed. Lets do this with a polygon pour.

Click Polygon.

Draw a box that follows the dimensional outline, left clicking on each corner.

When you close the box it will be come dashed. Now click on i and then on the dashed line. This will bring up information about the polygon.

We need to change the isolate from 0 to 0.012, click ok.

Why change the isolation layer from Eagles default? We have had multiple PCB fab houses, that produce very high quality PCBs, create polygon pours that accidentally run over onto a trace or pad. This error is rare, but we want to give the PCB fab house an easier job, not a harder one. Increasing the isolation pulls the polygon away from traces and pads just a smidgen, giving the PCB fab house a little more tolerance for error, and increasing the chance that your PCB will come in without errors.

Now to connect the polygon pour to the ground net, press F4 to go into Name mode. Then click on the edge of the polygon. Change the net name to GND.

Press F8 to refresh the rats nest. This also causes polygon pours to recalculate. Neat!

Now repeat for the bottom polygon pour. Click polygon, then click the middle scroll wheel and move to the bottom layer. Box the board. Change isolate to 0.012. Press F4. Name net to GND. Hit F8 to polygon refresh.

Yay! We have both bottom and top polygons connected to GND. Note the comment in the lower left corner of the window. Ratsnest: 2 airwires (hidden: 2 GND). Uh oh. Looks like we still have a few things to connect. Lets turn GND airwires back on. Click on the i, then click on the edge of the polygon. Uncheck Airwires hidden and click ok.

Yep. Thats a problem. Lets create a GND via to connect the various GND islands to the lower layer polygon.

Click on the Via button on the menu and drop the via in a GND island that needs to be connected. This via is not yet connected to GND - its unnamed. So press F4, then click again on the via. Name it GND. Now hit F8 for ratsnest refresh. Neat! One wire gone.

Now that we have a good GND via, we can copy it. Click on the copy button, then click on the GND via we just created. Youll have a via that is moving with your cursor. Move it towards the GND island on the right end of the board. Drop the via. Hit escape to leave copy mode. Hit F8 to refresh the ratsnest.

Yay! Ratsnest nothing to do! Weve successfully routed all the airwires. Next we need to label everything on the board.

Adding Labels

The default DRC rules with Eagle are a little too conservative in some areas, and very bad in others. Lets load the SparkFun dru file located here (need link!!). Click on the DRC button, then Load.

Double click the SparkFun.dru file then click Select in the main DRC window. It should disappear.

What? It looks the same. But wait!

Hit F8 to do a ratsnest refresh. That looks a little better! The SparkFun DRU file reduces the amount of space between the copper layers and the dimension layer (the border of your board) from 40mil to 10mil.

All these vias should work but they are pretty sloppy. The SparkFun design rules file increases the size of the annular rings around your vias. This gives the PCB fab houses a bigger ring to drill through the middle of, thus decreasing the chances the your board will be fabricated with errors.

Now lets increase the width of the board outline from 0 to 0.008. We do this so that we give the DRC (design rule checker) the chance to tell us if anything is too near the board edge. When the PCB fab house is routing boards apart, they use a very accurate milling machine, but lets assume theyre not perfect. We use the width of the board outline to give us that level of extra safety.

To change the width of the board edge click on the wrench, then width, then. Enter 0.008 then click on the board edge. It will probably highlight the polygon pours. To get around this, right click and the next thing in the stack will highlight - it will probably be the other polygon pour so right click again. Finally the white line that makes up the board outline should be highlighted. Good - now left click to apply the width change. Now do that to the other three sides.

Now its time to label everything! Click the Text button. A window will pop up, enter TX.

There will then be text on the bottom layer. No good. Click the middle mouse wheel and select tPlace. Anything on tPlace will be printed as silk. Hold the alt button and arrange the TX label next to the TX LED.

Pressing escape will bring you back to the text input window. Type RX and add the label next to the other LED.

See how the X of TX and RX is bisected? I like centering text. I threw these labels down but I dont actually know which LED is which. Lets consult the FT230X datasheet:

Ok, CBUS1 is RX LED, CBUS2 is TX LED. Lets go look at our schematic:

Oh no! I wired it wrong. Lets delete those two wires (press F3 then click on the wire to remove), group the LED/Resistor/GND (alt+F7 then select, then F7), move them down (ctrl + right click), and add wires back (F9).

Lets also label the nets so we will know on our layout which is which. Alt+F9 then click on a wire to add a label. Click again to anchor the label to the wire. F4 to rename the wire to RXLED (on CBUS1 pin). Repeat for CBUS2 wire label.

Ok fixed. Lets go back to our layout.

Weve got some crossed wires. Rip up the traces that were there, swap the LED placement with the alt-F7 group command then re-route.

Rerouted. Now press F12 to Show trace names and click on a trace. You will see the name of the net in the lower left corner of the Eagle window. TXLED is now labeled correctly.

Copy the TX label a bunch more times. Press F12 and click on each trace to figure out what is there (Remember when we named the nets on the schematic? Heres where it pays off). Then do a Change wrench -> Text and change each label to what each pin actually is.

Is the text size a little too large for your taste? You can use the wrench to change size as well. We prefer 0.05" or larger so that the text is easier to read.

Remember: the PCB fab house has limits to what it can do. Weve found that anything smaller than 0.04" turns into an unreadable white blob.

Now do some label centering. See those vias in the middle of the labels? The user will probably be able to read the label, but lets move the two vias in order to make the label unbroken.

Is moving vias out of the way of text unnecessary? I would argue it is necessary. The board only has value if you know how to hook up to it. And Im not talking about in the next week or two, Im talking about when youre soldering on a ladder using a head lamp and youre not sure which spot to solder the sensor to Clear labels make or break a project.

I am getting pretty happy with this layout. Lets add some finishing touches. Because were SparkFun, we throw our logo on everything. Were also a big proponent of the Open Source Hardware initiative. From the Aesthetics library, lets add two of the LOGO-SFE and one OSHW-LOGO.

I sometimes have to add some lines on the tDocu layer to show me center point on the board. I draw these in by hand then remove them once Ive used them to center a logo or text label.

This is version v1.0 of the board so add that text, in copper, to the bottom of the board. Hit F8 to ratsnest refresh and see the text in the bottom copper.

Now for some sanity checking. I have turned on all the layers to be sure that the vias will be tented (covered up by the solder mask). You can see in the screenshot that there are white hash marks on most SMD pads and on the large 0.1 connector on the end of the board. The smaller vias however to not have these hash marks. The DRC rules are set up (see the Mask tab under DRC) to mask over any hole 0.020 or smaller. I have added a larger via to show this point. This larger via would be exposed.

There are a few circumstances where we expose a via or two - usually for test points. We use a spring loaded pogo pin to make contact with that point on the board so that we can test the board more easily. But in general, all the vias on SparkFun boards are masked over for aesthetic reasons.

Lastly, we add the designers name to the PCB and schematic. This is to maintain attribution whenever the design gets reused or modified. Its also nice to know who to talk to if there are support questions.

Design Rule Check


Time to run DRC on the board to make sure weve not made any electrical or mechnical mistakes. Lets turn off the extra layers by pressing F11 and click on the DRC button, then Check.

Hmm Weve got some errors. This dimension error is because the annular ring of the connector is too close to the edge of the board. Remember when we increased the width of the board outline? This is being raised because of that. The risk here is that when the board is milled out it may nick the annular ring of this connector. SparkFun has a general policy that this is ok and this type of error, on a 0.01 connector can be dismissed. In the rare event that the ring is nicked, the connection and therefore the signal will survive. Click on Approved through all the dimension errors.

This is a valid error! Looks like I accidentally created two vias, right on top of one another when I was routing that really small airwire. To fix this, lets alt+F9 rip up and click on that via to see if we can remove one.

Weve removed the via but Eagle is trying to tell us (with a big X) that something is still wrong. Hitting F8 ratsnest refresh doesnt help, so Im going to rip up those traces and re-route.

I ripped up those traces, then rerouted. I then re-ran DRC and Eagle is now happy. Error cleared.

This is Eagle trying to tell us the trace width of this text is too thin. Normally fab houses dont want traces thinner than 8mil (0.008). This text violates that. Obviously, we and the fab house dont care if these traces are broken because v1.0 is for informational purposes, not for signals. But the real way to correct this is to increase the text ratio so that the traces get bigger than 8mil. Hit the i button, click on the text and increase the ratio to 20%. Re-run the DRC and the error should clear.

Ok. Were close to the finish line. Hit F8 and make sure there are no remaining airwires. Run DRC one last time to make sure there are no DRC errors.

I often turn off everything but the top layer and look at the trace routing. Are there any traces that do anything really silly? Then I do the same for the bottom layer.

Gerber Generation


This layout is done! Now lets generate some gerbers and get this board made! Hit F11 to turn on all the standard layers then click on CAM. If you dont have the SparkFun CAM file, grab it here and put it in your Eagle\cam directory or, what I recommend, is to put this CAM file on a Dropbox folder that way you use the same CAM file between different version of Eagle and different computers.

From within the CAM window, click on File->Open and located the sfe-gerb274X file. Once youve got the sfe-gerb274x.cam open, click Process Job. A few windows will pop up then close. Now go look in the folder that contains FT230X-Breakout:

The .brd and .sch files are the main Eagle files. If you want to post or share your design with a friend online, these are the two files you need to zip and send them.

All the files ending in *.b#1, .b#2, .s#1, .s#5, etc are backups. Every time you save the schematic or board Eagle will create a new b#_ file and save the previous brd file to it. This is handy if you need to revert back to a version you were working on.

The *.gpi (general photoplotter information) and *.dri (drill information) are generally not needed by the PCB fabrication house.

The main gerber files you need to grab:

*.GBL - Bottom copper layer
*.GBO - Bottom overlay (silkscreen)
*.GBS - Bottom soldermask
*.GTL - Top copper layer
*.GTO - Top overlay (silkscreen)
*.GTS - Top soldermask
*.TXT - Drill file (coordinate information)
Note there is no dimension file in this list. The dimension layer gets exported to the top copper layer using our CAM file. Your fab house can probably work with this but may want something different.

You will probably see a *.GTP file. This is the top paste layer. At SparkFun, we use this layer to have a paste stencil cut. Stencil solder paste and doing SMD reflow is super helpful if you are running more than 3 or 4 boards. You can absolutely stencil, build, and reflow PCBs without big, expensive equipment! And you can even cut stencils at home.

Select the gerber files and drill file, 7 in all. Do this by clicking on the first file, then hold Ctrl, then click on each additional file. Right click and under Windows 7 you can Send To a zip file. Zip together however you are most accustom.

I just recently found www.gerber-viewer.com. They have a pretty good interface for inspecting your gerber files. I highly recommend you use a gerber viewer separate from Eagle before you send them off.

With your gerber files in hand, email your favorite PCB fab house. Most fab houses are setup to do:

Silkscreen one side
Green soldermask
White silkscreen
1.6mm thick FR4 PCB
Almost all PCBs have these specs but doing fancier PCBs is getting cheaper and cheaper. All our products are made with red soldermask and have silkscreen on both sides. Our LilyPad line is 0.8mm thick with purple soldermask. If youre just doing protos, stick with the standard setup. If youre doing a production run, get creative!

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