SoCs and advanced packages (such as system-in-package or package-on-package), and the board layout are typically designed in separate environments. Information can be communicated and exchanged from SoCs across different toolsets using file formats such as OpenAccess and LEF/DEF. But due to the continued challenges of higher densities, miniaturization and reduced power consumption, design teams are finding it difficult to consider the complete system when they make critical decisions at each design stage. When a design reaches the package development stage, there are typically only minor modifications made to the IC’s floorplan or die bump location, but communicating these changes can be cumbersome and inaccurate. If amendments are required, they are usually driven by IC design teams, as there is a general impression that there is a large amount of flexibility in the connectivity between the chip and the package, but does this yield the best result? Only by looking at the interconnect as a system can this question be answered. Tradeoffs need to be understood and the impact on performance and package/PCB cost weighed.
This webinar is aimed to help the audience identify disconnects in the chip, package, and board design environment; and explore methods to optimize interconnects, improve design collaboration, and enable signal traceability and analysis across the complete system.
