Here simply constructed a "scene" , combined with the following figure explain to reflux and reflux as well as some cross- power division problems. To facilitate the mapping, the layer spacing enlarge.
A signal output terminal IC1 , IC2 is the signal input terminal ( To simplify the PCB model , assuming the receiving terminal includes resistors ) the third layer formation . IC1 and IC2 are from ground level to the third level . Top right corner of the top floor of a power plane , received a positive power supply. C1 and C2 respectively IC1, IC2 decoupling capacitors. Figure chip power and ground pin are shown in hair, received signal power supply terminal and ground .
At low frequencies , if the S1 -side output high , the entire current through the wire loop is connected to VCC power supply plane , and then by the orange path into IC1, then from S1 side out , along a second layer of wire end through R1 into IC2, then enter the GND layer , through the red path back to the negative power .
However, at high frequencies , the distribution characteristics of PCB signal presented will have a significant impact . We often say to reflux is a problem in the high-frequency signal often encountered. When the signal lines S1 to R1 has increased current , the external magnetic field is changing rapidly , the sensor causes a conductor near the reverse current. If the ground plane of the third layer is a complete ground plane , then will have a blue dotted line marked on the ground plane currents ; TOP layer if there is a complete power plane , it will be at the top there is a blue edge dashed back. At this point there is minimal signal loop current loop , the minimum energy radiating capacity external signal is also coupled to a minimum . ( High frequency skin effect also radiate energy minimum , the principle is the same. )
Because of the high frequency signal level and current changes very quickly , but the change cycle is short, the energy needed is not large, so the chip and off- chip decoupling capacitors recently taken power . When C1 is large enough and fast enough and the reaction (with low ESR values , usually ceramic capacitors . Ceramic capacitor ESR tantalum capacitors far below . ) , Located at the top of the orange path and located GND layer red path can as is ( the entire board , and there is a current corresponding to the power supply , not shown , but the current corresponding to the signal ) does not exist.
Thus , according to the figure constructed environment, the entire current path is : the C1 positive - Yellow > GND layer -> IC1 's VCC-> S1-> L2 signal line -> R1-> IC2 of GND-> vias path - > vias - > capacitor anode . Can be seen , the current in the vertical direction is equivalent to a brown current magnetic field is induced in the middle , while the surface of this ring can be easily coupled to the external interference. If the signal is a graph and a clock signal , a parallel set 8bit data line , the same chip by the same power supply , the current return route is the same. If the data line level simultaneously with the flip , then make the induction of a large reverse current , if the clock line is not a good match , then this is sufficient to produce lethal effects of crosstalk on the clock signal to the clock. High and low intensity is proportional to the absolute value is not such crosstalk and interference sources , but the interference source and the current proportional to the rate of change for a purely resistive load , the crosstalk current is proportional to dI / dt = dV / (T10% -90% * R). Formula dI / dt ( current change rate ), dV ( swing interference source ) and R ( load of the source of interference ) all refer to the parameters of the interference source (in the case of capacitive load , then , dI / dt is the T10% - inversely proportional to the square of 90% ). As can be seen from the formula, the low -speed signal may not be smaller than the crosstalk signal . This is what we say : Signal 1kHZ is not necessarily low-speed signals , and comprehensive consideration of the case along . For very steep along a signal containing many harmonic components , the frequency at the point has a large amplitude. Therefore , when the election should take note of the device , do not blindly choose the fast switching speed of the chip , not only high costs , but also increase crosstalk and EMC problems.
Or any other adjacent power plane layer , as long as both ends of the capacitor provides a suitable signal to a low reactance path GND , then the flat plane can be used as reflux of this signal . In the usual application, the corresponding transceiver chip IO power tend to be consistent, and generally have a 0.01-0.1uF decoupling capacitor between the respective power and ground , and these are precisely the two ends of capacitors in the signal, so that Recirculation is second only to the power plane ground plane . And use other power plane returning to do so, often do not have a low resistance path to ground at both ends of the signal. Thus, in the current induced in the adjacent plane will find the nearest capacitor back ground. If the " recent capacitor " from the beginning or end very far end , then this is also subject to reflow " trek " in order to form a complete return path , and this path is also adjacent to the signal return path , the same back in circulation and the interference effect of the road is the same , the crosstalk between signals is equivalent .
For some cross- power division can not be avoided , a high-pass filter can be divided in place jumper across the capacitor or RC in series (such as 10 ohm resistor string 680p capacitors, according to their own specific values to the signal type, namely to provide high-frequency return path , but also the low-frequency crosstalk isolation between each other plane ) . This may be related to the increase in the capacitance between the power plane , it seems a little funny , but it is certainly effective. If some of the words are not allowed on the specification , you can split the two planes were cited at the capacitor to ground.
For other planes do borrow reflux condition , it is best to appropriately increase the number of small capacitors to ground at both ends of the signal, providing a return path . However, this approach is often difficult to achieve. Because most of the surface space near the terminal chip resistors and matched gave decoupling capacitors occupy .
