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Controllable high-speed PCB design and electromagnetic compatibility

by: Feb 26,2014 924 Views 0 Comments Posted in Engineering Technical

PCB PCB board layout PCB design PCB manufacturing PCB production PCB layout

First PCB layout

In PCB design, layout is an important step to complete product design , it can be said in front of the preparations for it are doing throughout the PCB , layout design process to define the highest and most detailed tips , maximum workload . There are single-sided PCB layout wiring , double-sided and multilayer wiring wiring . Wiring there are two ways : automatic routing and interactive routing , automatic routing before , you can use the interactive advance more stringent requirements for wiring the input and output terminals of adjacent parallel edges should be avoided to avoid reflection interference. Necessary, add ground isolation , wiring two adjacent layers perpendicular to each other and parallel prone to parasitic coupling.

Routability automatic routing , dependent on good placement, routing rules can be pre-set , including bending frequency alignment , the number of vias , step number and so on. Usually the first to explore the type of cloth warp quickly to short-term connectivity , and then wiring labyrinth , first connect to the cloth wiring path for global optimization , it can disconnect the line has cloth as needed . And try to re- wiring to improve the overall effect .

The current high-density PCB design has been felt through-holes are not accustomed to , and it wastes a lot of valuable routing channels to solve this conflict , there has been blind and buried vias technology, which not only completed the role of vias many , but also save a wiring channel the wiring process is completed a more convenient, more smooth, more perfect , PCB board design process is a complex and simple process , in order to have a good grasp it , the majority of electronic engineering design needs personnel to their own experience, to get the true meaning .

A power supply , ground handling

Even the wiring throughout the completion of the PCB was very good, but the interference due to the power supply, ground caused by thoughtless , product performance will decrease , and sometimes even affect the success rate of the product. So for electrical , ground wiring to be taken seriously , the noise power generated by the ground to a minimum to ensure the quality of the product.

For each engaged in electronic product design engineering personnel who are aware of the reasons for the noise between the ground and power lines generated , is only made ​​to reduce noise suppression formula to express :

( 1 ) , is known to add between power and ground decoupling capacitors .

( 2 ) , try to widen the power , ground width , it is better than the power ground wire width, their relationship is : Ground > Power cable> signal line , usually the signal line width : 0.2 ~ 0.3mm, the most by thin width of up to 0.05 ~ 0.07mm, the power line is 1.2 ~ 2.5 mm PCB can be used for digital circuit ground wire to form a wide loop , constitutes a ground network to use ( analog circuit ground not so used )

( 3 ) , a large area with a copper layer is used as a ground on the PCB is not the place to spend all connected with the land use as a ground . Or made ​​of plywood , power , occupied the ground floor of each .

Handle 2 of the digital circuit and analog circuit

There are many functional circuit no longer a single PCB (digital or analog circuit ) , but by the digital and analog circuit consisting of a mixture . Therefore, when the wiring need to consider mutual interference between them, in particular to the line noise .
High- frequency digital circuits , analog circuits strong sensitivity to the signal line , the high-frequency signal lines as far away from the sensitive analog circuit devices on the ground , the whole people PCB is only one node to the outside world , so must be processed in the PCB inside of the mold to the problem, and on-board internal digital and analog ground is actually a separate disconnected between them , just outside the PCB and interface connections ( eg plugs , etc. ) . Digital and analog ground a little short , please note that there is only one connection point. There are no common ground on the PCB , which is determined by the system design.

3 on the power signal line cloth (ground ) layer in the multilayer printed wiring , since the signal line is not finished fabric layer is not much the rest of the line , and then more layers will result in increased production of waste will also give some workload , but also a corresponding increase in cost , to solve this conflict, can be considered in the electric wiring on the ( ground ) floor . Should first consider the use of the power layer , followed by the formation . Because the best is to retain the integrity of the formation .

Treatment 4 conductor connecting large leg

In large areas of ground ( power ) in connection with their legs commonly used components , to handle the connection leg needs to be comprehensive consideration , the electrical properties , the copper surface element leg pads and full contact as well, but element there is some bad welding assembly risks such as: ① welding requires high power heater. ② likely to cause Weld point . Therefore, both the electrical properties and process requirements , made crosswise pad , called thermal isolation (heat shield) , commonly known as heat pads (Thermal), so that welding can result in excessive heat generated sectional Weld points may greatly reduced. The same multilayer electrical connection (ground ) floor leg treatment.

Role of the network cabling system 5

In many CAD systems, network cabling system is based on the decision. Grid too dense , although access has increased, but the step is too small, too large field data map , which is bound to have more storage space requirements for the equipment , but also target computer electronics computing speed great impact. And some path is invalid, or if the mounting hole is a pad element occupies a leg , fixed holes are occupied and the like. Grid depopulation , little effect on the fabric path through a great rate . So there must be a reasonable density grid system to support wiring proceed.

The distance between the legs of the standard components of 0.1 inches (2.54mm), so that the grid system is typically based on the set to 0.1 inches (2.54 mm) or less than 0.1 inches of integer multiples , such as: 0.05 inches , 0.025 inches , 0.02 inch .

6 Design Rule Check (DRC)

After completion of wiring design , layout design needs to be carefully checked whether the rules established by the designer , but also need to confirm the rules established by the PCB production process meets the needs of the general examination of the following aspects :

( 1 ) , from line to line , line and component pads , line and through holes , pads and through-hole components , through-hole and through hole between reasonable, whether to meet production requirements.

( 2 ) , the width of the power line and the ground is appropriate, whether the tight coupling ( low impedance ) between the power supply and the ground ? Is there a place to make ground widened in the PCB .

( 3 ) , for critical signal cable is best to take measures, such as the length of the shortest line added protection , input lines and output lines are clearly separated.

( 4 ) , analog circuits and digital circuits , whether separate ground wire.

If ( 5 ) added to the PCB after the graphics ( such as icons, subscript ) will cause the short-circuit signal .

( 6 ) is not ideal for some linear modification .

( 7 ) , is added with the PCB process line ? Solder meets the requirements of the production process , solder size is appropriate, whether the pressure of the character logo pads on the device , so as not to affect the quality of Denso .

( 8 ) , the power frame edge multilayer formation is reduced, formation of the copper foil is exposed as the power supply is likely to cause short-circuit -board .

The second PCB layout

In the design, the layout is an important part. Layout results will directly affect the wiring of results, so it can be considered reasonable PCB design layout is the first step to success.

Layout are two ways , one is an interactive layout , another is automatic layout , usually on the basis of automatic layout adjustment with an interactive layout in the layout can be re- door circuit traces according to the situation distribution , and the two exchanged gates , making it the best layout for easy wiring . After the layout is complete, but also on the design documents and related information return label on the schematic , PCB board makes information about the schematic is consistent with the order in the next filing, design changes can be synchronized together , while the simulation for information to be updated , which allows for the electrical performance and functionality of the circuit board-level verification.

- Consider the overall appearance

A successful product or not, it is necessary to pay attention to the intrinsic quality , and second, taking into account the overall appearance , both of which can be more perfect that the product is successful.

In a PCB board layout elements required to be balanced, density and orderly , not top-heavy or a head sink .

- Check the layout

PCB size is consistent with the processing of paper sizes ? Ability to meet the PCB manufacturing process requirements ? Whether the anchor tag ?

Components on a two-dimensional , three-dimensional space with or without conflict ?

Density component layout is orderly, neat ? Whether all fabric finish ?

Require frequent replacement of components can be easily replaced ? Plug-in boards inserted into the device is easy ?

Profile between the thermal element and the heating element proper distance ?

The adjustable element convenience ?

The need to heat the place , installed a radiator does not ? Air flow is smooth ?

The signal flow is smooth and interconnection shortest ?

Are plugs, sockets, etc. and mechanical design conflicts ?

Interference problems have to consider whether the line ?

Third high-speed PCB design

Challenge ( a ) , an electronic system designed to face

As system design complexity and improve the integration of large-scale , electronic systems designers are engaged in more than 100MHZ circuit design , the operating frequency of the bus has reached or exceeded 50MHZ, some even more than 100MHZ. Currently about 50 % of the design of the clock frequency than 50MHz, nearly 20 % of the design frequency exceeds 120MHz.

When the system is operating in 50MHz, will have integrity issues and signal transmission line effects ; whereas when the system clock reaches 120MHz, unless the use of high-speed circuit design knowledge , otherwise PCB design based on traditional methods will not work . Thus , high-speed circuit design techniques have become designers of electronic systems design tools must be taken . Only through the use of high-speed circuit designers design techniques to achieve the controllability of the design process.

(B ) What is the high-speed circuit

If the frequency is usually considered digital logic circuits meet or exceed 45MHZ ~ 50MHZ, and work on this frequency circuit has accounted for some of the weight of the entire electronic system ( for example, 1 / 3 ) , it is called high-speed circuits.
In fact , the frequency of the harmonic signal edge than its high frequency signal , the signal changes rapidly rising and falling edges (or signal transition ) of the signal transmission caused unexpected results. Therefore , if the line is generally agreed propagation delay is greater than 1 /2 of the drive-end digital signal rise time, such a signal is considered a high-speed signal transmission lines and the effect produced .

Instantaneous signal transmission occurs in the signal state change , such as the rise or fall time . From the drive signals to the receiver after a fixed period of time , increase the transmission time is less than 1/ 2 or fall time , the reflected signal from the receiving end will arrive before the end of the driving signal changes state . Conversely , the reflected signal will reach the signal changes state after the drive end . If the reflected signal is very strong, it may be superimposed on the waveform of the logic state change .

OK ( three ) , high-speed signals

We define the preconditions above transmission line effects occur, but how that line delay is greater than the signal rise time of 1/2 drive end ? Generally , a typical value of the signal rise time can be given by the manual device , and the signal propagation time is determined by the actual length of the wiring on the PCB design. The following figure shows the signal rise time and allow the wiring length ( delay ) correspondence.

PCB board inch per unit delay is 0.167ns.. However, if the hole is too much, the device pins and more constrained set of multi- line network , the delay will increase. Signals are usually high-speed logic devices rise time is about 0.2ns. If the board has a GaAs chip , the maximum wiring length is 7.62mm.

Let the signal rise time Tr , Tpd propagation delay of the signal line . If Tr ≥ 4Tpd, signal falls safe area. If 2Tpd ≥ Tr ≥ 4Tpd, signal falls uncertain area. If Tr ≤ 2Tpd, signal falls problem areas. For fall uncertain regional and regional signals , high-speed wiring method should be used .

(D ) What is the transmission line

Traces on the PCB can be modeled as shown below capacitors, resistors and inductors in series and parallel structures . Typical values ​​for the series resistance 0.25-0.55 ohms / foot, as the insulating layer because of the parallel resistor is usually high. After the parasitic resistance , capacitance and inductance added to the actual PCB connection , the connection is called a final impedance characteristic impedance Zo. The wider diameter , from the power / ground closer , or the higher the dielectric constant of the insulating layer , the smaller the characteristic impedance. If the impedance of the transmission line and the receiver do not match , then the output current signal and the signal of different final stable state , this causes the signal at the receiving end of reflection , the reflected signal will return the signal transmitter and reflected back again . With the weakening of the amplitude of the reflected signal energy will decrease , until the voltage and current signal to stabilize. This effect is called oscillation , the oscillation signal at the rising and falling signals can often be seen .

( Five ) , transmission line effects

Defined above transmission line model, summed up the whole circuit transmission line design will bring the following effects.

• Reflected signals reflected signal

• delay and timing errors Delay & Timing errors

• repeatedly across the logic level threshold error False Switching

• Overshoot and undershoot Overshoot / Undershoot

• Crosstalk Induced Noise (or crosstalk)

• EMI radiation of electromagnetic radiation

5.1 reflected signal

If a trace is not properly terminated ( termination ) , the pulse signal from the drive end is reflected at the receiving end does not lead to the desired effect on the distortion of the signal profile . When distorted very significant errors can lead to a variety of causes designed to fail. Meanwhile, the distorted signal is increased sensitivity to noise , will cause the design to fail. If the above is not sufficient to consider the case , EMI will be significantly increased, which results not only affect their design , will result in failure of the entire system.

Mainly due to the reflection signal is generated : long traces ; not match the end of the transmission line , excessive capacitance or inductance and impedance mismatch .

5.2 delay and timing errors

And timing error signal delay as follows: a period of time the signal transition in the signal does not change the logic level between the high and low thresholds. Excessive signal delay timing errors may lead to confusion and device functions.
Usually when there are multiple receiving end will have problems. Circuit designer must determine the worst-case time delay to ensure that the design is correct. Reasons for the delay signal generated : drive overload, traces too long.

5.3 times the threshold level beyond logic error

Signal transition process may span multiple logic level threshold which leads to this type of error . Across multiple error threshold logic level is a special form of the oscillation signal , i.e., the oscillation signal of the logic level occurs in the vicinity of the threshold , the logic level crossing times will cause the logic threshold dysfunction . The reason of the reflected signal : long traces , not the end of the transmission line , excessive capacitance or inductance and impedance mismatch .

5.4 overshoot and undershoot

Overshoot and undershoot or signal line is too long to go from changing too fast for two reasons . Although the receiving end of most of the components have input protection diode protection , but sometimes these overshoot component level will far exceed the supply voltage range , damage components .

5.5 Crosstalk

Crosstalk performance of the signal line with a signal through the PCB adjacent to the signal line will induce a signal about called crosstalk.

The closer the ground signal line , the greater the spacing , the smaller the crosstalk signal. Asynchronous and clock signals are more prone to crosstalk. So the solution is to remove the signal crosstalk occurs shielded signal crosstalk or serious interference.

5.6 Electromagnetic Radiation

EMI (Electro-Magnetic Interference) that is EMI problems of excessive electromagnetic radiation comprises electromagnetic radiation and the sensitivity of the two . EMI performance of the system when the digital power operation, the ambient electromagnetic radiation would thus interfere with the operation of the environment of the electronic device . The main reason is that it produces high operating frequency of the circuit and the layout is unreasonable. At present, conducted EMI simulation software tools , but are expensive EMI simulator , simulation parameters and boundary conditions are very difficult to set up , which will directly affect the accuracy and usefulness of the simulation results . The most common approach is to control the various EMI design rules in every aspect of the design , realization rules on the design and control of all aspects of driving .

( Six ) , a method to avoid the transmission line effects

In response to these problems affect the transmission lines are introduced , we talk about ways to control these impacts from the following aspects.

6.1 strict control of key trace cable length

If the design of high-speed transition edge , we must take into account the effect of the presence of the transmission line on the PCB problem. Now widely used in high frequency clock is fast IC chip there is a problem . Solve this problem there are some basic principles: If using CMOS or TTL circuit design, the operating frequency of less than 10MHz, the wiring length should not exceed 7 inches . Operating frequency at 50MHz wiring length should be no more than 1.5 inches . If the operating frequency of 75MHz to meet or exceed the wiring length should be 1 inch. GaAs chip for maximum wiring length should be 0.3 inches . If you exceed this standard, the existence of the problem of the transmission line .

6.2 rational planning traces topology

Another way to solve the transmission line effect is to choose the right path and terminal wiring topology . Topology refers to the alignment of the order routing and wiring structure of a network cable . When the high-speed logic devices, unless the length of the branch traces remain very short, otherwise the edge is rapidly changing signal traces the main branch of the signal traces are distorted. Under normal circumstances , PCB traces are two basic topologies , namely daisy chain (Daisy Chain) cabling and star (Star) distribution .

For daisy chain wiring , wiring from the drive end Start, reach each receiver. If using a series resistor to change the signal characteristics , the series resistance should be located close to the drive end . In the control traces harmonic interference , the daisy chain alignment best. But this cabling mode lowest pass rate , 100% of the cloth is not easy to pass . The actual design, we are making a daisy chain wiring branch lengths as short as possible , the length of the value of the security should be : Stub Delay <= Trt * 0.1.

For example , high-speed TTL circuit branch with a length of less than 1.5 inches . This topology is small wiring space occupied by a single resistor and can be matched to an end. However, this is not the wiring pattern such that a different synchronization signal in the received signal at the receiver .

Star topology can effectively avoid the problem of the clock signal is not synchronized , but the high density wiring is completed manually on the PCB is very difficult. Automatic routing is the best way to accomplish star wiring . Require termination resistors on each branch . Termination resistor should match the characteristic impedance of the connection phase . This can be calculated by hand , but also to calculate the characteristic impedance value and the termination resistor value by CAD tools.

In the two examples above use a simple terminal resistance , in practice the option of using more complex matching terminals. The first option is to match RC terminal . RC matching terminal can reduce power consumption, but can only be used in the work of a relatively stable signal . This method is best suited to match the clock line signal processing . The disadvantage is that the RC terminal matching capacitance may affect the shape and the propagation velocity of the signal.

Series resistor matching terminal does not produce additional power consumption, but will slow down the transmission of the signal. This way little impact for the time delay bus driver circuit . Series resistor matching terminals advantage lies in the connection can reduce the number and density of the board using the device .

Finally, a way to match the terminal for the separation in this way the matching member to be placed in the vicinity of the receiving end . The advantage is not low signal , and can be good to avoid noise. Typical for the TTL input signal (ACT, HCT, FAST).

In addition, the termination resistor package types and mounting types must also be considered . Typically SMD surface mount resistors than through-hole components with lower inductance , so the element of choice SMD package . If you choose , there are two common line resistance of installation options : vertically and horizontally .

Vertical mounting in a mounting pin of the resistor is short , can reduce the thermal resistance between the resistor and the circuit board , the heat resistance more easily into the atmosphere . But the longer vertical mounting will increase the resistance of the inductor. Installation by the installation of the lower level has a lower inductance. But overheating resistance drift appears , in the worst case where the resistivity becomes an open circuit , causing the failure of the matching end of the PCB traces , as potential causes of failure .

Method to suppress electromagnetic interference 6.3

A good solution to the problem will improve the signal integrity of PCB electromagnetic compatibility (EMC). Which is very important to ensure that the PCB has a good ground . Designed using a complex signal with a ground plane layer is a very effective method. Furthermore , the density of the outermost circuit boards minimum signal also a good way to reduce electromagnetic radiation , this method can be " surface layer" "Build-up" system designed to make PCB to achieve. By increasing the surface area of ​​a thin insulating layer and a porous layer through which the ordinary process to achieve a combination of PCB , resistors and capacitors can be buried in the subsurface , walking the line density per unit area nearly doubled , thus reducing the volume of the PCB. Reduce PCB area has traces of topology huge impact , which means narrowing of the current loop , narrow branch trace lengths , and electromagnetic radiation is approximately proportional to the current loop area ; while the small size means high -density characteristics cited pin package devices can be used, which in turn makes the connection length decreased , thereby reducing the current loop to improve the electromagnetic compatibility characteristics .

6.4 Other techniques can be used

To reduce the power supply voltage integrated circuit chip transient overshoot, decoupling capacitors should be added to the integrated circuit chip. This can effectively remove burrs and to reduce the impact on the power supply in the power supply loop PCB radiation .

When the decoupling capacitor directly connected to the power management integrated circuit is connected to the legs instead of the power supply layer , its smooth burr best. This is why there are some devices socket with decoupling capacitors , and some devices require decoupling capacitors distance from the device to be small enough .

Any high-speed and high- power devices should be placed together to reduce supply voltage transient overshoot .

If there is no power planes , so long power connection is formed between the signal and loop the loop and become easy radiation sensing circuit .

Traces form a line does not pass through the same network conditions or other traces of the loop is called open loop . If the loop through the same network cable other traces constitute a closed loop . In both cases, the formation antenna effect ( wire antenna and a loop antenna ) . External antenna generates EMI radiation , but also sensitive to its own circuit . Closed Loop is an issue that must be considered , because the radiation it produces a closed loop is approximately proportional to the area .


High-speed circuit design is a very complex design process , ZUKEN company's high-speed circuit routing algorithm (Route Editor) and EMC / EMI analysis software (INCASES, Hot-Stage) applied to the analysis and discovery issues . The method described in this paper is designed for high-speed circuit design to solve these problems . Moreover , during high speed circuit design several factors need to be considered , and sometimes opposite to each of these factors . As the layout position near the high-speed device , can be reduced although the delay, but may produce significant thermal crosstalk effects. Therefore, in the design , the need to weigh the various factors that make a comprehensive trade-offs ; both to meet the design requirements , and reduce design complexity. Speed ​​PCB design using configuration means the design process controllability , only controllable , is reliable , and can be successful !

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