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Design Custom IoT Protocols & Gateways ------iotSDR

by: Aug 13,2020 3370 Views 0 Comments Posted in Activities

IoT Protocols & Gateways iotSDR PCBWay Crowd Supply IoT radio network domains LoRa

If you are looking to build their very own Internet of Things protocols and gateways, you may be interested in a new versatile development board called the iotSDR.

iotSDR provides a platform that allows SDR developers and enthusiasts to develop cutting-edge solutions in the IoT radio and network domains. 

Equipped with two narrow-band Microchip AT86RF215 frontends the development board is capable of providing I/Q streams and modem functionality for the Xilinx ZYNQ SoC, as well as a MAX2769 GNSS chip for custom GPS, Galileo, BieDou, and Glonass development. It is also compatible with the popular GNURadio SDR software.

If you want to design and develop a physical layer protocol for IOT – a protocol like LoRa, SigFox, WightLess, Bluetooth, BLE, 802.15.4, ZigBee, or something of your own – this board is for you. It is also a great place to start if you want to build a custom IoT gateway along the lines of The Things Network, LPWAN, or Google Thread.

Features & Specifications

RF Transceiver: 2x Microchip/Atmel AT86RF215

  • European band: 863-870 MHz / 870-876 MHz / 915-921 MHz
  • Chinese band: 470-510 MHz / 779-787 MHz
  • North American band: 902-928 MHz
  • Korean band: 917-923.5 MHz
  • Japanese band: 920-928 MHz
  • World-wide ISM band: 2400-2483.5 MHz

GNSS Receiver: Maxim MAX2769B supporting GPS, GLONASS, Galileo, and BieDou

SoC: Two options available

  • Xilinx ZYNQ XC7Z010-1CLG400C

Dual-core ARM Cortex-A9 MPCore

256 kb on-chip memory

DDR3 support

28,000 logic cells

17,600 LUTs

2.1 Mb block RAM

80 DSP slices

2x UART, 2x CAN 2.0 B, 2x I2C, 2x SPI, 4x 32-bit GPIO

FPGA configuration via JTAG

  • Xilinx ZYNQ XC7Z020-1CLG400C

Dual-core ARM Cortex-A9 MPCore

256 kb on-chip memory

DDR3 support

85,000 logic cells

53,200 LUTs

4.9 Mb block RAM

220 DSP slices

2x UART, 2x CAN 2.0 B, 2x I2C, 2x SPI, 4x 32-bit GPIO

FPGA configuration via JTAG

EEPROM Memory: 1x Microchip AT24MAC602 for RF transceiver MCU firmware and data

Flash Memory: 1x QSPI 128 Mb flash memory for firmware

RAM: 512 MB DDR3

SD Card: Micro SD card slot

General User Inputs/Outputs:

  • 2x 8-bit PL (Programmable Logic) interfaces
  • 1x 8-bit PS (Programmable Subsystems) interface


  • 1x Gigabit Ethernet
  • USB 2.0 High Speed (Microchip USB3310)
  • USB 2.0 Full Speed (Silicon Labs CP2104)
  • 2x SMA RF connector for Low Frequency IoT band
  • 2x SMA RF connector for 2.4 GHz band
  • 1x SMA connector for GNSS receiver
  • FPGA JTAG connector for external JTAG programmer/debugger

Clock System:

  • Single clock source for both RF frontends
  • Separate clock for GNSS receiver

Board Dimensions: 76.2 mm x 101.6 mm

Block Diagram

It is currently in the crowdfunding stage on the Crowd Supply. Once the crowdfunding is completed, as the partner of the Crowd Supply, PCBWay will manufacture and assembly this board. Go for supporting it if you are interested in it!

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