Introduction
If you do not follow some basic layout guidelines , PCB design will limit the D class amplifier performance or reduce its reliability. Class D amplifiers are described below for some good PC board layout practices. Using STA517B with two BTL output ( 175 watts per channel ) digital power amplifier as an example , but for all Class D amplifier , the basic concept is the same.
Figure 1 : Stereo Class-D power amplifier schematic BTL
Ground plane
The ground plane is the key to good quality Class D amplifiers layout. If possible should the underlying circuit board ground plane as a proprietary , full ground plane can provide the best performance and most reliable design . If you have a circuit board in the bottom of the cloth signal lines or power traces should be as short as possible . If necessary , in order to trace the underlying short distance , the line should go back to the top of the board lead to avoid long distance at the bottom of the alignment .
Use vias top layer circuit board device and circuit board connected to the bottom of the ground plane . However , over the hole current will flow back to the ground plane blocked , so flexibility is required to use these vias.
In the area directly below the required amplifier copper . If the amplifier at the bottom of its package has an exposed pad or plug-ins , then the IC must be soldered to the decentralization of the amplifier , the amplifier can be used as a fan so hot zone . In this case, the land must be under the direction of the positive sides from the IC leads , so you can make sure that their nudity. The amplifier to be marked with the following many vias through thermal vias to the underlying circuit board fan , so it can be used as a fan hot zone .
Just below the amplifier is not recommended to go signal lines. Shall play several vias and the ground plane connected directly to ensure a low impedance path to ground reference point for all the devices to each other. This output filter is particularly important . All filters have a direct path to be returned to the ground plane beneath the amplifier .
Supply bypass capacitor
To ensure the stability and noise and crosstalk suppression , plus the power supply bypass capacitor is very important. Amplifier's output stage to absorb a lot of current, and switching rapidly. When the output switching , the parasitic inductance bypass capacitor between the power input pin and the amplifier will produce a lot of glitches , so the parasitic inductance must be kept as small as possible . In order to reduce the effect of stray inductance and bypass capacitors between the resonant power stage of the amplifier should be required to use 1uF capacitor in parallel with a 100nF capacitor at each power input pin.
100nF capacitor and the IC must be as close as possible ( usually no more than 2 mm ) . Also shown in Figure 1 , a bypass capacitor and the IC must be in the same layer in order to reduce the total path length ( and stray inductance ) . 1uF capacitor must be placed in sequence , and 100nF capacitor close together .
Figure 2 : Using the bottom of the circuit board for the 100nF capacitor connected , so would significantly increase the total trace length and the board will have a negative impact on performance .
Needs using a large volume storage capacitor in the power amplifier input decoupling. Bulk storage capacitance is dependent on the amount of current required amplifier . Bulk storage capacitors and amplifiers, and power pins must be connected to the star , and the amplifier must be as close as possible ( ideally less than 30 mm ) .
100nF bypass capacitor must be placed close to the IC
Figure 3:100 nF bypass capacitor must be placed close to the IC .
Figure 4:1 uF capacitor should be placed after the 100nF capacitor , 1uF capacitors through vias and board the underlying ground plane connections.
Buffer
Buffers pieces shall then be placed in a peripheral portion of the bypass capacitor . The output from the amplifier via a buffer to the bypass capacitor ground return path must be as short as possible ( or differential forms will be returned to the buffer amplifier ) .
Figure 5 : Buffer pieces required subsequent placement. The chart below shows the layout of a differential buffer , the figure is a buffer between the two pieces of a BTL amplifier output terminals connected directly without connecting any ground .
Figure 6 : This diagram shows the layout of a common-mode buffers , each buffer is connected to the output and ground . Common mode and differential buffer buffer can provide better performance compared .
Power electrolytic capacitors
Electrolytic capacitors and filter inductor must be placed after the buffer. Electrolytic capacitors and high voltage power supply is required for all IC input pin is placed as close as possible .
Figure 7: electrolytic capacitor layout
Between electrolytic capacitors and amplifiers must be a "star" connection , which can reduce the effects due to another amplifier and capacitor connected to the same voltage drop caused . Between the daisy chain multiple power amplifiers will cause noise, crosstalk and stability issues , even with a wide trace mode to no avail .
If the class D amplifier IC circuit board than a , each IC must have their electrolytic capacitors. If there is more than one of the electrolytic capacitors, electrolytic capacitor that is connected between the power supply is also sure to be a star way .
In short , such as VCC and the output signal path to handle high current traces Always wide and short as possible , so you can fully reduce trace resistance and inductance . VCC and output traces with high voltage and high current , so they must stay away from sensitive signals and devices, such as clock and PLL so on.
Output Filter
Always followed by the output filter element . The output from the amplifier to the inductor and the path from the power film capacitor was carrying a large current with a large number of high frequency components , so the path must be as wide and short, thus reducing the stray resistance and inductance .
Inductor and the amplifier must be placed as close as possible , but also between adjacent inductor to maintain a certain distance. If the open magnetic inductor is to suppress electromagnetic interference between the inductor should be at least 7.5 mm distance from each other , especially between the different channels of the inductor and even more so .
Figure 8: Layout output filter components and high-frequency current path
The output filter components and traces the location is crucial to reduce EMI . Low- pass filter , the walking loop area between the lines must be as small as possible . Single- ended output amplifier , the ground return path amplifier is therefore subject to a small loop area . As long as the board has a good ground plane can be required to implement this point .
For BTL amplifier with output , the filter area is the area of the loop connecting the IC traces , filter inductance and capacitance between the film ( see Figure 5 ) . In order to reduce the loop area , BTL output filtering traces must be parallel to each other and as much as possible to retain some trace spacing. However , each individual channel output traces may not necessarily adjacent to each other .
Low-pass filter capacitor and common mode filter inductor items must be as close as possible . With a single-ended output amplifier for , DC blocking capacitor must then be placed . And speakers connected to the output connectors and filters must closely as possible the layout .
Figure 9: four-channel single-ended amplifier output layout examples
Circuit board layout recommendations are summarized
Device layout Priority:
1) 100nF supply bypass capacitor
2) 1uF supply bypass capacitor
3 ) buffer pieces
4 ) electrolytic capacitors
5 ) Output filter member
100nF and 1uF decoupling capacitors must be placed as close as possible and IC . Spacing between 100nF capacitor and IC must be less than 2 mm . In order to reduce the trace lengths and lower stray inductance , 100nF capacitor and its connection to the IC must be the same layer of the circuit board and IC in .
100nF capacitor must be stacked X7R ceramic chip capacitor (MLC). 1uF capacitor must be tantalum or X7R multilayer ceramic chip capacitor.
Snubber network must be as close as possible and IC layout . Using a rating of at least 100V X7R ceramic capacitors , and to ensure that the capacitor can handle the power consumption.
From electrolytic capacitors to the power traces IC requires the use of a star connection .
Power supply and output traces must be short and as wide as possible in order to reduce the stray resistance and inductance .
Close the output signal path routing in order to reduce the loop area ; while maintaining the filter element and the IC is placed as close as possible .
In the top of the circuit board layout of the circuit as much as possible , and the best as the underlying circuit board ground plane. Only in the case of last resort before the signal lines and power lines go at the bottom of the board, and must be flexible to use vias.
The amplifier input low voltage circuits away from the power amplifier output circuit
Whenever you have the use of surface-mount devices as possible . SMT devices have lower parasitic inductance ( on the bypass capacitor performance is particularly important )
Class D amplifier devices require manual layout , do not use automatic placement and routing software.
In short , in order to reduce the resistance and inductance , high current handling traces such as VCC and the output signal path must be as wide and short. VCC and the output signal traces still has a higher voltage and current, so these must be away from the sensitive signal traces and sensitive devices, such as a clock signal and PLL devices.
