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DDR2-800 for PCB signal integrity design and DDR3

by: Mar 04,2014 6314 Views 0 Comments Posted in Engineering Technical

PCB layers PCB

This article relates to the design of DDR2 and DDR3 PCB (PCB) , the signal is considered a matter of design and power integrity , which is a considerable challenging . Focus is discussed in the article as few PCB layers, especially in the case of 4 laminates under related technologies, some of which design methods have been proven in the past been used .

1 Introduction

Currently , more generally, the use of high speed DDR2 has 800 Mbps, and even higher speeds , such as 1066 Mbps, and has high speed DDR3 1600 Mbps. For such a high speed , from the perspective of the design of PCB , to be strict timing matched to meet the integrity of the waveform , there are many factors to consider all these factors affect one another are , however, there are some personality between them , they can be classified as laminate PCB , impedance network topology , delay matching , crosstalk, power integrity and timing , at present, there are many EDA tools they can be well calculated and simulation, which Cadence ALLEGRO SI-230 and Ansoft's HFSS use more.

Table 1 shows the DDR2 and DDR3 has a total of proprietary technical requirements and technical requirements .


Table 1: DDR2 and DDR3 requirements more

2. PCB laminate (stackup) and impedance

For PCB layers bound by a substrate (eg, 4 shelves) , all of which signal lines can only go in the TOP and BOTTOM layer , intermediate layers , one of which is GND plane layer , and another layer of VDD plane layer , Vtt and Vref at VDD plane layer wiring . When using the alignment layer 6 , a special topology design easier , and because the spacing layer and the Power GND layer becomes small, thus improving the PI.

Another parameter impedance interconnect channel DDR2 designs in constant time must be continuous, single-ended impedance matching resistor 50 Ohms traces must be used on all single-ended signals and achieve impedance matching , and for differential signals , 100 Ohms impedance matching termination resistors must be used in all of the differential signal terminals, such as CLOCK and DQS signals. In addition, all matching resistor must be pulled up to VTT, and remains 50 Ohms, ODT setting must also be kept at 50 Ohms.

In the DDR3 design , the terminal single-ended signal matching resistance between 40 and 60 Ohms alternative is designed to ADDR / CMD / CNTRL signal line , which has been shown to have many advantages. And, on the termination resistor pulled VTT SI simulation results based on trace impedance , resistance values ​​may need to make different choices , often the resistance value between 30-70 Ohms. The impedance matching resistors differential signal is always at 100 Ohms.


Figure 1: four-and six-way PCB stack

3 Internet access topology

For DDR2 and DDR3, which signal DQ, DM and DQS are point to point interconnect , so no topology, however, outside the column is not in the multi-rank DIMMs (Dual In Line Memory Modules) design such . When peer manner , can easily be done by the ODT impedance impedance settings to achieve the waveform integrity. For the ADDR / CMD / CNTRL and a number of clock signals , which are multi-point connectivity needs , so you need to select an appropriate topology, Figure 2 lists some relevant topology in which Fly-By topology is a daisy -chain specific , it does not require a long connection may not be necessary or even short (Stub).

For DDR3, all of these topologies are applicable , however, a prerequisite traces as short as possible . Fly-By topology in dealing with noise , with good waveform integrity , however, is difficult to achieve on a 4- layer board , laminates require six or more, and daisy chain topology on a 4- layer board is easy to implement the . Furthermore , the tree topology requirement length AB and AC length is very close ( Figure 2 ) . Considering the waveform integrity, and as much as possible to improve the branch trace lengths , but also to meet colleagues constraint requires board layer, 4 layer board based DDR3 design, is the most reasonable topologies with a minimum short-term (Stub ) daisy chain topology.

Figure 2: With two of SDRAM ADDR / CMD / CNTRL topologies

For DDR2-800, which are applicable to all topologies , but there is little difference . However, the daisy-chain topology is proved advantageous aspect SI .

For more than two of SDRAM, generally , are placed in different ways according to the device and select the appropriate topology. Figure 3 shows the topology of different ways and specially designed placed in these topologies , only the A and D are the most suitable for 4-layer PCB design . However, for the DDR2-800, which are listed in topologies can meet the integrity of the waveform , while DDR3 design, especially in the 1600 Mbps when D is only designed to satisfy .


Figure 3 : With four of SDRAM ADDR / CMD / CNTRL topologies

Match 4 delay

When do the matching delay , often using the trombone in the way of wiring traces addition, there will be inevitable in the wiring layer when switching board , then it will add some vias. Unfortunately , all of these curved alignment with the traces and vias , are straightened into the ideal length of the alignment or the like, in which case they are unequal delay , shown in Figure 4 .


Examples Trombone and Vias : Figure 4

Obviously , the above- mentioned aspects of the same trombone way delay unequal straight lines is well understood , and the alignment with vias becomes more apparent . In the case of the centerline length equal , trombone delay traces straight line than the actual delay is small to come , and for alignment with vias , and delay is to be big . This delay is generated , there are two ways to solve it . One approach is needed only in EDA tools in precise delay matching calculation , then walked the length of the line of control on it. The other method is within the acceptable range, reduce mismatch .

For trombone line delay by increasing the asymmetry of the length L3 is reduced because there will be coupling between the parallel lines , the detailed results can be clearly seen through the simulation SigXP Figure 5, L3 ( in Fig. different S) length will result in different delays , the longer length as S , the delay can be reduced more unequal . For microstrip line is , L3 more than seven times the distance to the alignment is necessary .


Figure 5 : For the simulation circuit and the simulation waveform trombone

trombone delay line is coupled to it by the parallel lines , and between the effect without the need for an increase in the pitch , and can reduce the degree of coupling of the saw tooth wire is used . Obviously , saw tooth line than trombone line with better results , but it needs more space. Due to the possible delay caused by different reasons , therefore, the actual design, by means of CAD tools for rigorous calculation , thereby controlling the delay matching traces .

Factors to consider in Figure 6 in the through-hole plate 2 , when a signal is too close to the ground via hole placement , the delay in terms of the impact must be considered . For the first example , the length of the microstrip line TOP layer is 150 mils, also a microstrip line BOTTOM layer 150 mils, a line width are 4 mils, and the hole is through the parameter : barrel diameter = "8mils", pad diameter = "18mils", anti-pad diameter = "26mils".

There are three options to consider comparison , one is by no ground vias too close to the hole interconnection vias , then its return path only through vias 250 mils from the edge of the PCB to provide ; second yes, a microstrip line up to 362 mils ; third is around a signal line has four ground vias surrounded . Figure 6 shows a conventional 60 Ohm line with the S-Parameters, it can be seen from the figure, with four ground vias surrounding the signal via the S-Parameters as a continuous strip line , thereby improve the S21 features. It can be seen in the vicinity of the signal return path via the absence of circumstances , this would greatly increase the signal via its impedance. Today's high-speed system, it is particularly important in terms of delay .

Now do a test circuit similar to Figure 5 , the rising and falling edges of the drive source is a linear trapezoidal signal output impedance of 60 Ohms , and the signal are 100 ps, ​​the amplitude of 1V. This signal source in three ways as shown in Figure 6 , and its termination to a load 60 Ohms , which is a periodic excitation signal a of 800 MHz . 0.5V at this point, we observe the time delay from the source to the receiving end between the displayed delay differences between them . The results are shown in Figure 7 , the figure shows only the rising edge of the signal from the figure can clearly be seen, with the four holes through the surrounding ground through the孔时延compared with only 3 ps linear , and in the absence of ground vias surrounding its delay is 8 ps. It can be seen , an increase in ground vias surrounding the signal via hole density is helpful . However, in 4 layers of PCB in , this would seem not entirely feasible , due to its signal line is close to the power plane , which makes the return path signal is determined by the degree of coupling between them to decide. So, in 4-layer PCB design , in order to meet the power integrity (power integrity) requirements, control over the degree of coupling is very important.


Figure 6: s-parameters with a through-hole interconnection channels


Figure 7: send and receive waveforms in Figure 6 three cases

For DDR2 and DDR3, the clock signal is transmitted in the form of differential , while DDR2 Lane , DQS signals are single-ended or differential mode communication depends on the rate of work , when you work with a high rate differential approach. Obviously, the same length , the switching delay is less than a single line of the differential end of the wire . According timing simulation results , the clock signal and DQS may need more than the corresponding ADDR / CMD / CNTRL and DATA lines a little longer. In addition , you must ensure that the clock and DQS cloth which in its associated ADDR / CMD / CNTRL and DQ lines. Since DQ and DM transmission at high speed, so , the need for each one byte , the length of which must be strictly matched , and can not have vias. Differential signal sensitivity of impedance discontinuity is relatively low, so for layer alignment is not much problem in the wiring priority cloth clock and DQS.

5. Crosstalk

In the microstrip line, the crosstalk is a very important factor to produce the delay. Typically , you can increase the distance between the parallel microstrip lines to reduce crosstalk interaction , however , go on-line in the rational use of space which is a great disadvantage , therefore, should be controlled within a reasonable range inside. A typical rule is to walk the line and trace spacing greater than twice the distance to the ground plane . Further , ground vias also play a very important role in Figure 8 shows the degree of coupling with the ground and not the land of the via -hole , in the case of a plurality of ground vias , which reduces the degree of coupling 7 dB. Taking into account the cost of Internet access in the budget for both sides for proper simulation is necessary when adding a periodic excitation in all the wire will jitter generated by the signal crosstalk , through simulation, the signal can be observed in the time domain jitter, thus through rational design , considering the space and signal integrity, selecting the optimal alignment spacing.


Figure 8: coupling traces s-parameters

6 Power Integrity

Power here refers to the integrity of the maximum signal switching , the tolerance of the power . When tolerance does not meet this requirement will result in many problems, such as increased clock jitter, jitter and crosstalk.

Here, you can go to a good understanding of the theory and even related discussions from now on " target impedance " is defined formula.

Ztarget = Voltage tolerance / Transient Current (1)

Here , the key is going to be understood in the worst case switching transient current (Transient Current) effects , another important factor is the frequency switching. In all of the frequency range , the decoupling network must ensure that its impedance is equal to or less than the target impedance (Ztarget). On a PCB, capacitor constituted by the power and ground , and all of the decoupling capacitors , must be able to ensure the decoupling of about 100KHz between about 100-200MH to . Frequency 100KHz or less , a large capacitor voltage regulator module where you can be very good for decoupling. The frequency at 200MHz or more , you should by a dedicated on-chip capacitor or packaged capacitor decoupling. The actual power integrity is quite complex , which should take into account the switching frequency of the IC package and PCB power consumption simulation signal network . For PCB design, the target impedance decoupling design is relatively simple , and it is more practical solution.

In the design of DDR There are three power supplies, they are VDD, VTT and Vref. VDD tolerance requirement is 5% , while the instantaneous current from Idd2 to Idd7 different sizes , are described in detail in JEDEC . By plane capacitor and a number of dedicated power planes decoupling capacitors, power integrity can be done , including decoupling capacitor from 10nF to 10uF different sizes , a total of 10 or so. In addition , surface-mount capacitor is the most appropriate, it has a smaller resistance welding .

Vref requirements more stringent tolerances resistance, but it carries a relatively small current . Obviously , it requires a very narrow line to walk , and by twelve decoupling capacitors can achieve the target impedance requirements. Since Vref is very important that the decoupling capacitors are placed as close to the device pins .

However, VTT wiring is a considerable challenge , because it is not as long as there are strict tolerances , but also there are a lot of transient current , but the size of this current can be very easy to be calculated. Ultimately, by increasing decoupling capacitor impedance matching to achieve its objectives .

4 PCB laminates , the spacing between the layers is relatively large , thus losing the advantage of its power supply capacitance between the layers , so the number of decoupling capacitors will be greatly increased, especially high frequency of less than 10 nF capacitor . Detailed calculations and simulations may be implemented by EDA tools.

7. Timing Analysis

For the calculation and analysis of the timing of some of the relevant literature in a detailed introduction, eight areas listed below and analysis need to be set :

1 Write established analysis : DQ vs DQS.

(2) Write Hold analysis : DQ vs DQS.

3 Reading establish Analysis : DQ vs DQS.

4 Reading remain Analysis : DQ vs DQS.

5 Write establish Analysis : DQS vs CLK.

6 Write Hold analysis : DQS vs CLK.

7 Write established analysis :. ADDR / CMD / CNTRL vs CLK

8 Write Hold analysis :. ADDR / CMD / CNTRL vs CLK

Table 2 gives an establishment for writing (Write Setup) analysis examples. Tables need to get some data from the controller and memory manufacturers, paragraph "Interconnect" data is taken from SI simulation tools. For all of the above eight DDR2 are to be analyzed , and for DDR3, and 6 5 need not be considered . PCB design , the length tolerance aspects must ensure total margin is positive .

Table 2: For the DDR3 DQ vs DQS write to keep the time-domain analysis of case


8. PCB Layout

In the actual PCB design, taking into account the requirements of SI , tend to have a lot of compromise. Typically, the need to give priority to those of the signal integrity requirements of relatively high . When drawing PCB, when some of the relevant factors to consider , then the PCB design for reliability will be higher .

1 First, the relevant EDA tools in the set to be set up in the topology and associated constraints.

2 The BGA pin breakout , the ADDR / CMD / CNTRL pin disposed in the middle of DQ / DQS / DM byte group , because all of these groups operate , in order to signal the cross as little as possible , and some individual pin may be wiring is switched to other areas .

Crosstalk simulation results from the 3 . Shows that minimize the short-term (stubs) in length. Typically , short-term (stubs) can be reduced , but not all pins are done. Between the BGA pad and the pad may need only two memory traces can be achieved , but this must be a very fine line to walk , then it increases the production cost of the PCB, but not all traces only need two , unless the use of tiny holes through the hole and disk technologies . In the end, taking into account the tolerance and cost signal integrity may choose a compromise solution.

4 The Vref Vref decoupling capacitors close to the pin placed ; Vtt decoupling capacitors placed in an outer end farthest SDRAM ; VDD decoupling capacitors need to be close to the device. Decoupling capacitor capacitance values ​​require little closer to the device. Proper decoupling design, not all of the decoupling capacitors are placed close to the device . After all of the decoupling capacitors are required fanout pin alignment , thus reducing the impedance , typically , the home fans at both ends of the line segment will be perpendicular to the capacitor wiring .

5 When switching plane layers , as far as possible to match the length and add some ground vias , these EDA tools in advance should be well simulated. Typically , the time domain analysis, the two differential lines in the delay line to be matched to ensure that the error in the + / - 2ps, while the other signal is to be + / - 10 ps.


Before the introduction of majority rule in the PCB are suitable for containing one or more DIMM, outside is the only column in the DIMM in the decoupling factor to take into account the same distinction in DIMM group. In DIMM group , the topology for the ADDR / CMD / CNTRL was adopted with few short daisy-chain topology and tree topology structure is applicable.

10. Case

The rules described above, in the DDR2 PCB, DDR3 PCB and DDR3-DIMM PCB inside , have been widely used. In the following cases, we use MOSAID 's controller, which provides operating functions DDR2 and DDR3 . In the SI simulation , the use of the IBIS model, the model of memory from MICRON Technolgy, Inc, a model for the DDR3 SDRAM provide speed of 1333 Mbps . Here, the data operation is under 1600 Mbps . For unbuffered DIMM (unbuffered) of (MT_DDR3_0542cc) EBD model from Micron Technology, all waveforms are based on the following general test method , and the SDRAM die stage is calculated and simulated . 2 shown in Figure 6 laminates , the only TOP and BOTTOM layer wiring , consists of two pieces of SDRAM memory in a way that constitutes a daisy chain . In the case of DIMM , only one DIMM is used without caching . Figure 9-11 is TOP / BOTTOM layer wiring diagram of a flash photograph and signal integrity simulation of Fig .


Figure 9: Only in TOP and BOTTOM layer simulation waveforms walk the line of DDR3

( Left is ADDRESS and CLOCK network , the right is DATA and DQS network , its clock frequency 800 MHz, data communication rate 1600Mbps)


Figure 10: TOP and BOTTOM layers only walk the line of DDR2 simulation waveforms

( Left is ADDRESS and CLOCK network , the right is DATA and DQS network , its clock frequency 400 MHz, data communication rate 800Mbps)


Figure 11: TOP and BOTTOM layers only walk simulation waveforms of the line DDR3-DIMM

( Left is ADDRESS and CLOCK network , the right is DATA and DQS Network )

Preferably, Figure 12 shows two data signal after comparing the eye , is a simulation result, and the other is the actual measurement. In all the above cases , the perfect level waveform integrity are exciting .


Figure 12: 800 Mbps DDR2 simulation data signal eye diagram ( red ) and measured eye diagrams ( Blue )

11 Conclusion

In this paper , the design for a variety of factors , SI and PI of DDR2/DDR3 have done a comprehensive introduction. For four shelves in design to 800 Mbps DDR2 and DDR3 is feasible, but for DDR3-1600 Mbps is a great challenge .

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