Wiring (Layout) is one of the most basic PCB design engineer job skills. Traces will directly affect the performance of the whole system, most high-speed design theory should ultimately be achieved through the Layout and verify, we can see that the wiring is critical in high-speed PCB design. The following will address some of the situations that may be encountered in the actual wiring, analyze its rationality, and give some more optimal alignment strategy.
The main alignment from the right angle, the differential go three lines, serpentine lines to elaborate.
1 right angle alignment
Right angle alignment is generally avoided as far as PCB wiring requirements, but also almost become a standard measure of the quality of the wiring, then right-angle signal transmission traces what would have much impact? In principle, at right angles to the line will go The width of the transmission line is changed, resulting in impedance discontinuities. In fact, not only is the right angle alignment, Breton, acute traces are likely to create a situation where impedance changes.
Walking the line at right angles to the impact of the signal is mainly reflected in three aspects:
One corner of the transmission line can be modeled as a capacitive load, slowing the rise time;
Second, impedance discontinuities will cause the reflected signal;
The third is at right angles to the tip of EMI generated.
Right angles to the transmission line caused by the parasitic capacitance can be calculated following empirical formula:
C = 61W (Er) [size = 1] 1/2 [/ size] / Z0
In the above formula, C is the equivalent capacitance of the corner means (unit: pF), W represents the width of the trace (unit: inch), εr represents the dielectric constant, Z0 is the characteristic impedance of the transmission line. For example, for a 50 ohm transmission line (εr of 4.3) for a 4Mils, with a capacity to bring about a right angle to 0.0101pF, the rise time can be estimated and then the resulting amount of change:
T10-90% = 2.2 * C * Z0 / 2 = 2.2 * 0.0101 * 50/2 = 0.556ps
As can be seen by calculating the capacitance effect caused by a right angle alignment is extremely small.
Due to increase in line width at right angles to go, where the impedance will decrease, so will have some signal reflections, we can calculate the impedance of the transmission line sections mentioned formula to calculate the equivalent impedance of the line width increased, and then reflection coefficient is calculated based on the empirical formula:
ρ = (Zs-Z0) / (Zs + Z0)
Usually Cartesian impedance changes due to traces of between 7% -20%, thus the maximum reflection coefficient of about 0.1. Also, you can see from the figure, in the W / 2 length of time the transmission line impedance changes to a minimum, and then through W / 2 hours and returned to normal impedance, impedance changes occur throughout a very short period of time, often in the 10ps inside, so slight changes fast and signal transmission in general is almost negligible.
Many people have such a right angle alignment understand that the tip is easy to transmit or receive electromagnetic waves generated EMI, which has become one of the reasons many people think can not be at right angles to the alignment. However, many of the actual test results show that right-angle alignment does not produce obvious EMI than a straight line. Perhaps the current instrument performance, test level restricts the accuracy of the test, but at least it shows a problem, right-angle traces of radiation have been less than the measurement error of the instrument itself.
Overall, right-angle alignment is not quite that terrible. At least in the application below GHz, any such capacitors, reflection, EMI and other effects it produces in TDR test almost not manifest, high-speed PCB design engineers focus should be placed on or layout, power / ground design, alignment design, Other aspects, such as vias. Of course, despite the impact of right-angle alignment does not bring very serious, but it does not mean that we can go after the right-angle lines, attention to detail is necessary for each outstanding engineer basic qualities, and, with the rapid development of digital circuits, PCB signal processing frequency engineers will continue to improve, to more than 10GHz RF design, these small right angle speed may become the focus of the problem.
2 differential traces
Application of high-speed differential signal circuit design (Differential Signal) and more widely, the most critical signal circuits often have a differential structure design, so it is what other acclaimed it? And how to ensure its PCB design Good performance? with these two issues, we discuss in the next section.
What is the difference signal? Layman's terms, the drive-side transmission is two equivalents inverted signal, the receiving end by comparing the difference between the two voltages to determine the logic state "0" or "1." The differential signal carrying traces of the pair is called the differential traces.
Ordinary differential signals and single-ended signal traces compared to the most obvious advantage is reflected in the following three aspects:
a. interference ability, because the two coupled differential go well between the lines, outside the presence of noise when almost simultaneously coupled to two lines, and the receiver is only concerned about the difference between the two signals, So outside of the common mode noise can be completely eliminated.
b. can effectively suppress EMI, the same token, the opposite polarity of the two signals, they can be offset by the external electromagnetic radiation to each other, the more tightly coupled electromagnetic energy into the outside vent less.
c. timing positioning accuracy due to the change switch is located on the intersection of the differential signal of the two signals, rather than relying on an ordinary single-ended signal to judge the level of the two threshold voltages, and thus subject to the process, a small influence of temperature on the timing errors can be reduced , but also more suitable for low-amplitude signals on the circuit. Currently popular LVDS (low voltage differential signaling) refers to such a small amplitude differential signal technology.
For PCB engineers, the most concerned about is how to ensure the alignment of the actual differential traces can take full advantage of these benefits. Perhaps as long as people will come into contact with Layout differential traces to understand the general requirements, that is, "and so long, equidistant." Isometric is to ensure that the two differential signals of opposite polarity keep reduce common-mode component; equidistance is mainly to ensure consistency between the differential impedance to reduce reflections. "As close to the principle of" one of the differential traces is sometimes required. But all of these rules are not used mechanically, many engineers do not seem to understand the nature of high-speed differential signal transmission. The following highlights the differential signal PCB design discuss several common myths.
Myth one: that the differential signal does not require a ground plane as a return path, or that the differential traces for each other to provide reflux way. The reason for this misunderstanding is a surface phenomenon confused, or for understanding the mechanism of high-speed signal transmission is not deep enough. Configuration of the reception side can be seen from FIG 1-8-15, the transistors Q3, Q4, the emitter current is equivalent to the reverse, they cancel each other exactly at the ground current (I1 = 0), so that the differential circuit Similarly, shells, and other may exist on the power and ground planes are not sensitive to noise signals. Reflux offset portion is not representative of the ground plane to the reference plane is not the differential circuit as the signal return path, in fact, the signal return analysis and differential traces go ordinary single-ended line mechanism is the same, i.e., the high frequency signal is always minimum reflux along the loop inductance, the biggest difference is that in addition to the differential line coupled to the outside, there is coupling between them, what kind of coupling is strong, it has become a major return path. Figure 1-8-16 geomagnetic field is a single-ended and differential signals in the distribution diagram.
In the PCB circuit design, general differential coupling between traces smaller, often only 10 to 20 percent of the coupling, more or coupling ground, so the main return path differential traces still exist in the ground plane . Local plane discontinuity occurs when an area without reference plane, the difference will go coupling between the lines provide the main return path, as shown in Figure 1-8-17. Despite the reference plane discontinuities impact on the differential traces no ordinary single-ended traces to the serious, but still reduce the quality of the differential signal, increasing the EMI, should be avoided. Some designers also believe that you can remove the differential line below the reference plane to go to suppress partial differential transmission of common mode signal, but in theory this approach is not desirable, how impedance control? Do not give a common-mode signal ground impedance circuit, is bound to cause EMI radiation, this approach more harm than good.
Myth: think more important than keeping equidistant line length matching. In the actual PCB routing, often can not meet the design requirements differential. As the pin distribution, vias and traces of space and other factors exist, must reach the line length matching purposes winding through appropriate talent, but the result is bound to bring some areas of the differential pair is not parallel, this time how do we choose? Before we take a look at the following conclusion following the results of a simulation.
It seems from the above simulation results, Options 1 and 2 are almost coincident waveform, ie, the impact caused by unequal spacing is minimal, comparatively speaking, does not match the length is much greater impact on the timing (Option 3). From the theoretical analysis, then, although it will result in inconsistent spacing differential impedance changes, but because the difference between the coupling itself is not significant, the impedance range is very small, usually less than 10%, only one had equivalent hole caused by reflection, which is the signal transmission will not cause significant impact. Once the line length does not match, in addition to the timing offset occurs, the introduction of a differential signal back to the common mode component reduces the signal quality and increase the EMI.
So to speak, PCB design differential traces the most important rule is to match the line length, the other rules can be flexible according to the design requirements and practical applications.
Myth: consider the differential traces must rely on the close. Let the differential traces close is simply to enhance their coupling, can enhance immunity to noise, but also make full use of the magnetic field of opposite polarity to offset against external electromagnetic interference. Although in most cases this approach is very beneficial, but not absolute, if we can guarantee them adequately shielded from outside interference, then we would not need to let interference by each other to achieve strong coupling and the purpose of suppressing EMI. How can we ensure that the differential traces with good isolation and shielding it? Increases and other signal traces of pitch is one of the most basic ways, electromagnetic energy is diminishing relationship with the square of the distance, the general line spacing over four times the line When wide, interference between them on extremely weak, and can be ignored. Furthermore, by isolating the ground plane can also play a very good shielding effect, this structure at high frequencies (10G or more) IC packages often use PCB design adopted is called CPW structure can ensure strict differential impedance Control (2Z0).
Differential traces can also go in a different signal layers, but generally do not recommend this walk because of the different layers such as impedance resulting difference vias will destroy the effect of differential mode transmission, the introduction of common-mode noise. In addition, if two adjacent coupling is not tight enough, it will reduce the ability to resist the differential traces of noise, but if we can maintain the proper alignment and spacing around, crosstalk is not a problem. In general the frequency (GHz or less), EMI will not be a very serious problem, experiments show that apart 500Mils differential traces of radiation energy in three meters beyond the decay has reached 60dB, enough to meet the FCC standards for electromagnetic radiation, so Designers do not have to worry too much about the differential lines caused by electromagnetic coupling enough incompatibilities.
3. Serpentine line
Is a kind of serpentine traces often used in Layout mode. Its main purpose is to adjust the delay, designed to meet the system timing requirements. The designer must first have this understanding: serpentine line will destroy the signal quality, change the transmission delay, to try to avoid the use of wiring. But the actual design, in order to ensure sufficient retention time signal, or to reduce the time offset between the signals in the same group, often have intentional winding.
So, serpentine lines are for signal transmission affected? When traces should pay attention to what? Among the most critical parameter is the two parallel coupling length (Lp) and coupling distance (S), as shown in Figure 1-8-21 shown. Obviously, the signal transmission serpentine traces coupling occurs between the parallel segments, the form of a differential mode, S smaller, Lp is larger, the greater the degree of coupling. May result in reduced transmission delay and crosstalk due greatly reduce the quality of the signal, the mechanism can refer to Chapter III of the common mode and differential mode crosstalk analysis.
