IP or intellectual property is an organization’s valuable asset which is often developed by a design engineer’s vision of the bus structure together with its relationship with its components, while also capturing and designing logic.
However, there is often a separation between a digital designer’s visions of the bus structures on PCBs. And more often than not, the capturing and the routing of this vision are not done efficiently.
Commonly, designers communicate IP in hand drawn documents as there are no available tools that can provide effective support in successfully capturing and communicating IP. Although a hand drawn idea can be captured quickly, several factors might make it impossible to map physically to the PCB. Size issues such as the physical width of the bus, the mechanical parameters of the card, along with the pin-outs and physical size of the components are common issues designers face.
An original IP might be impossible to follow physically as there is a lack of EDA tools that can successfully replace, improve, communicate, and capture a usable IP all throughout its design process.
An accurately captured IP requires collaboration throughout its remaining design flow. This can greatly shorten the timeframe of the design as it prevents the re-entry of intellectual property by others. Also, with the use of the same IP, the intent which was made originally is successfully maintained. This effectively removes misunderstandings and other types of errors as well as increases the efficiency in the design flow.
Planning and Capturing Topology
The use of a topology planning tool allows the design engineer to capture and define the bus structure as well as effectively communicate it in the design flow. In order for the bus structures to be effectively planned, they must first be logically defined so that its topology can also be accurately captured.
The tools used in capturing topology should be accurate and flexible in providing visual feedback. Not to mention, these tools should also be easy to use and intuitive. The capturing process should start with an exact representation of bus paths in order to ensure what the design engineer is capturing fits into intended PCB sections. If this capturing process is not followed, the IPs integrity might not fully translate.
Proper component placement is crucial as it greatly affects the bus structure. The efficient planning of topology must successfully support the component’s placement by buses. While on the placement process, the designers are able to place and filter these components that are sharing a bus.
Even though it is considered as flexible, a bus structure which is “packed” does not function with all topology planning scenarios. If there is not enough room for a packed structured, an unpacked area for the bus is considered as a better solution.
Signal delays can also be created by timing concerns and these can consume tons of trace space on a PCB. The proper estimation of the required space and the proper planning to where tune delay lengths should be added are crucial solutions.
Planning for unexpected problems like SI issues can also help shorten the design cycle of a PCB. This will also help designers achieve the needed signal performance while also successfully sharing IP in PCB designs.
