Global electronic design innovation leading corporate Cadence design systems inc. (NASDAQ: CDNS), recently announced the latest edition of the Allegro ® printed circuit board (PCB) technology, to solve customer for efficient product development need to simplify the solution. Allegro 16.6 to high speed interface timing closure speed up 30-50%, it depends on the temporal sensitive physical implementation and verification, its corresponding to the industry's first electronic CAD (ECAD) team work environment, to use Microsoft SharePoint technology in PCB design.
"Chip designer's task is listed on the pressing time limit the development of increasingly sophisticated products, quickly and easily call for local and international design team and resources, will bring great competitive advantage," Microsoft innovation and product lifecycle management solutions director Simon says Floyd, "Cadence ® PCB design tools and SharePoint integration, provides a unique environment, promote teamwork, create and control design, productivity will get great improvement."
Allegro 16.6 line of the new features will help embedded double-sided and vertical component miniaturization, improved time-series sensitive physical implementation and verification, to speed up the timing closure, and improve the ECAD and mechanical CAD collaborative design (the direction of MCAD) - all of these is very important to speed up the development of multi-functional electronic products.
Allegro suite industry leading PCB design miniaturization function was launched in 2011. Allegro 16.6 product suite to continue using the embedded active and passive components of the latest production technology, solve the problem of shrinking about the specific design of circuit board size. Components can use the Z axis vertical to infiltrate layer of PCB, greatly reduce the size of the X and Y wiring.
"We are leading ECP (C) technology to satisfy the customer demand for the miniaturization of cost savings," senior AT&S encapsulation, chief operating officer Mark Beesley says, "the Cadence and AT&S has many years of cooperation, is now solve the needs of customers for advanced miniaturization technology together."
Allegro 16.6 interact through automatic delay adjustment (AiDT) to speed up the time sequence sensitive physical implementation. Automatic interaction delay adjustment can shorten the time to meet the high standard interface timing constraints, such as DDR3, shorten the extent to which can be up to 30-50%. AiDT can help user interface to quickly adjust the key one time of high speed signal level or applied to the bytes channels, adjust the line on the PCB from a few days time shortened to a few hours. EMA Timing Designer combined with Allegro PCB SI function, help the user to quickly implement key high speed signal Timing closure.
PCB/enclosure is to simplify the process of collaborative design through the ECAD - the direction of MCAD, based on proStep iViP standard EDMD schema version 2.0. This process can reduce unnecessary iteration between ECAD and the direction of MCAD team, shorten product development time.
Supply: Allegro PCB solution 16.6 will be released in the fourth quarter of 2012.
