How to Design the PCB Board

With the initial requirements and constraints determined, several choices must be made. A compromise is made between the available materials, the required current requirements, board thickness, and an estimate of the number of layers and trace and space.

• Open new file or load appropriate template.

• Check for standards in pads, vias, or text styles.

• Draw board border using .040" line on center.

• Draw all slots/cutouts in board using .040" line on center.

• Enter design information.

• Load libraries/archived library.

• Load netlist.

• Generate BOM and compare against parts list. (This is to include mechanical components not in the schematic.)

• Place parts with a predefined location where necessary.

• Define classes/nets with trace width, clearance (space), and hole clearance.

Selecting Material Thickness and Copper Weight

Determining which material to use for double-sided boards is simple enough. Standard materials come in two basic configurations: multilayer core and double-sided core. ML core material is measured by core material separate from the copper thickness. DS core material is measured overall, including the copper thickness. Figure 5-1 displays a board stack-up that is 10% less than the available space in the enclosure shown in Figure 5-2.

Note

The term stack-up refers to the representation of the order the materials placed. Lay-up refers to the physical placement of the material preformed by the manufacturer.

Determine Copper Thickness

The copper thickness can be selected by initial copper thickness and design to the constraint (thickness) or by determining the thickness requirements from the circuit current/voltage requirements and some of the controlling space requirements. Figure 5-3 displays spacing constraints, one of the controlling factors/limitations for a sample board.

After some general routing or knowledge of the board is known, a determination of some of the trace requirements can be made. If possible, use 1/2 oz copper to start with and go from there.

An example circuit is only 5 V but carries 3 Amps of current. 5 V only requires .001"[.0254] of space, but the technology constraints require a minimum of .006"[.1524] (both sides). The spacing requirements for Figure 5-3 are only .020"[.508]. Subtracting .012"[.3084] (.006"[.1524] on either side) only leaves .008"[.2032] for a trace. As shown in Table 5-2, a .008"[.2032] trace at 1/2 oz can only handle a little over .2 Amps, so the copper thickness must be increased to 1 oz.

Another option would be to reduce the pad size, if the servicing requirements allowed. In this example, the pads are at their minimum allowance.

Spacing between the leads and pads of a component is one of the common determining factors in copper thickness and technology.

Note

The accompanying software allows the designer to calculate the pad size and, using pad spacing, trace width, and spacing, show the number of traces allowed between the pads.

Defining Trace/Width

Whether a schematic was completed or not, the circuits or nets must be defined for current and voltage. Current is relative to a square inch of copper for a particular temperature. The square inch of a trace is defined by a trace's width and the thickness of the copper it is etched from. The third determining factor is the temperature increases above room temperature. First a desired temperature is selected. This is a temperature that is desired for an "across-the-board" value. If it causes no increase in layers or square inch required for the board, 0°C should be selected. A compromise between available copper thickness and available trace width is made based on combinations available for the temperature requirements.

For all jobs, the initial trace selection should be a considerable amount more than what is necessary and above that of the minimum amount for the technology. An example would be for the advanced technology, which is a .006"; therefore, a .008" trace would be preferred, allowing for reduction when necessary. It is not necessary to use the minimum trace width for the current rating unless space is tight.

Current and square inch are not linear due to the increase of heat. This means that there is no simple multiplier for the calculation.

Standardizing Trace Width

Standardizing trace width may seem bizarre, but ease of route and consistency are a large payoff in the end. When spacing is a concern, the designer will know the necessary room to route several traces because of familiarity with trace width, clearance, and multiple trace width. Although external and internal traces and clearances can be different, unless space is very tight, a worst-case scenario may be used. As mentioned earlier, less space is necessary internally due to higher insulation, but more trace width is necessary to dissipate heat since the internal trace is enclosed; thus a compromise may be reached. For the worst-case type routing:

• Use the internal trace width.

• Use the external clearance.

(This practice is fairly common, and "define by layer" attributes are not available in some lesser quality software.)

Grid routing is also extremely important. Many designers continue to prefer a more aesthetic board, which may require grid routing. For inch grids, multiples of 6 are quite common. Example: .025" grid using a .012" trace leaves a .013" clearance, or effectively 1:1 ratio (12/12).

If using a .001" grid, .006" is the common minimum trace, for 1/2 oz copper. (Refer to Table 5-4 for minimum t/s per technology/copper thickness.)

Selecting the Dielectric Material

Copper thickness is initially selected, and then dielectric material is selected based on availability. These are the values that determine core thickness:

• Overall thickness

• Pre-Preg material thickness

• Available materials

• Copper thickness

Simultaneously, the copper thickness, Pre-Preg, and core thickness per layer can be calculated to determine what cores available may be used as shown in Figure 5-4.

Note

In the accompanying software, stocked material may be recorded to determine material use.

Figure 5-5 provides an example material table used to track available thickness, configuration, and tolerance per material type.

Defining Copper Thickness, Trace Width, Number of Layers, and Technology

All designs hinge around the current and voltage requirements and the components used. The minimum trace and clearance is not desired because it will usually change/increase technology and cost. The attempt is to stay with a lower technology while keeping the design routable. The board may be populated with components before defining the width and clearance. How small the width and clearance needs to be depends on the clearance between pins on many of the components. Most of the decisions will be made from experience, but without experience, trial and error is next.

Anytime during the design, the number of layers may be increased or decreased. If any of these elements falls below the limits of the technology and falls into a higher technology, the entire design may as well be within that technology.

With that in mind, the width and clearance can be defined and routing attempted. If the routing fails, then either the layers or the technology should be increased. By increasing the number of layers (a much simpler choice), no other attributes need be increased and the design continues. If increasing the number of layers is not an option or the design is already at the maximum number of layers for that technology, then the technology should be increased.

By increasing the technology, the following options may change:

• Width decreases

• Clearance decreases

• Pad diameter decreases

• Aspect ratio increases

• Via holes size decrease

• Via pad size decreases

• Number of layers increases

It is obvious that either initially determining the correct technology or increasing the number of layers is very important and time saving.

Determining material and copper thickness and trace widths becomes less complicated after time when standards are set and common stack-ups are determined. Most boards a designer will make will use 1/2 oz copper material for all layers. This is the most common material and has the greatest number of different thicknesses. Keeping this in mind, most designs will start with these values. Board thicknesses of .031 and .062 are the most common because the "core" materials stocked are in .031 multiples (.031, .062, .093 etc.). If not a single-sided or double-sided board, multilayer boards are either built to a desired thickness or to one of the .031 multiples. Designing to these values provides consistency and standardization. Using these values, all trace width and clearance calculations can then be determined. Just because a trace width can be .006" or .005" doesn't mean it should be designed that way.

Trace width and clearance should initially be at least .002" larger than the smallest width and clearance for that technology. This will allow the designer to decrease the width and clearance to the technology limit before changing technologies.

Selecting the component with the densest pattern, such as a PGA, BGA, or a dense connector, and then attempting to route this area first can help determine the width and clearance before too much work is done. Often components such as these will determine the technology of the board. Table 5-3 is an expandable quick list of components and the technology of the board used. These are generalities and, like most generalities, have exceptions. For SMT, the generality is that if the designer requires SMT, then room is most likely a concern. Although SMTs may be used on conventional technology boards, advanced is usually used. Components such as BGA(s) usually require leading edge because of the number of pins that are grouped together and the need for the traces to exit the area.

For example, a BGA that has six rows to the center in advanced technology may require at least five signal layers to exit the component area, whereas a leading-edge technology board would allow half that amount.

Many components require a certain level of technology if they are used. Table 5-3 shows some common components and the required technology use.

Table 5-4 shows a quick list of the technologies. Table 5-5 shows a table of changes to be made when increasing the technologies.

• Define other design attributes or design rules.

• If applicable, define class trace and space by layer.

• Configure design/job for

• Overall design rules

• Mask swell (global)

• Paste swell (global)

• Plane swell (global)

• Pad swell (global)

• Thermal divide (pad dia./4)

• Thermal clearance

The Pad and the Thru-Hole

Understanding the manufacturing and assembly constraints and considerations allows the designer to determine the proper pad surface area. IPC has specifications for minimum annular ring, but these are minimum possible values and should not be used unless necessary. IPC specifies .002" external and .001" internal minimum annular ring. This value should be over the hole wall. The AR shouldn't be the same size as the hole wall plating, since the external pad behaves like a cap for the hole wall and helps ensure that the hole wall will stay in place. With most technologies the manufacturer requires an additional pad so the hole wall is guaranteed to have some pad area, as shown in Figure 5-6.

Defining the Thru-Hole

Holes and thru-holes have been traditionally broken up in two groups: plated (supported) and non-plated (unsupported) holes. The term supported refers to the plating in the hole wall. Non-plated or unsupported holes may or may not have a pad such as a mounting hole and no hole wall plating (Figure 5-7). This is manufacturing terminology but for designing the holes should be broken up in two categories of soldered and non-soldered.

In each of those categories the classification of plated and non-plated should be identified.

• Soldered

• Plated thru-hole (PLTH) (including vias)

• Non-plated thru-hole (NPTH)

• Non-soldered

• Plated thru-hole (PLTH)

• Non-plated thru-hole (NPTH) with and without pad

The designer must know if the pad is identified as soldered or non-soldered first. This information helps the engineer to determine if the pad calculation should be for soldering or for the minimum annular ring. If the pad is unsoldered, a standard AR can be applied and doesn't change according to assembly requirements.

Note

A via is simply a plated thru-hole that isn't soldered. It does not require a calculation to determine pad size per assembly or application, but rather a simple calculation of the minimum annular ring or the smallest, most cost-effective size that can carry adequate current.

Non-Soldered Thru-Hole

Minimum annular ring (or Min. AR) comprises two different terms. A manufacturer, when talking about a Min. AR, is speaking of the Min. AR required by the standards or specification the designer has noted, plus its own AR requirements. The specified annular ring, from IPC or other standard, is the minimum AR required for board completion. Table 5-6 displays the minimum possible AR regardless of specifications. This value should not be used but rather a more realistic value.

This value is for vias or non-soldered pads and should not be used with soldered pads. Remember that the AR is only 1/2 of the pad diameter. To accomplish this, the manufacturer requires additional pad area to account for the errors of its process: imaging, drill, and registration, as shown in Figure 5-6 and Table 5-7. In conventional technology each of these is about .003" Therefore, the manufacturer's AR must be added to the pad:

        Non-soldered total AR = finished AR + manufacturer's AR
              Example: .0025" + .009" = .0115" Total AR

To find the total diameter, the total AR of this value must be multiplied by 2:

        Total diameter = total AR x 2
        Example: .0115" x 2 = .023"

Now that the pad requirements have been found, the finished hole diameter must be added to find the overall pad diameter:

        Finished pad dia. = total diameter + finished hole diameter
                    Example: .023" + .008" = .031"

Therefore, the minimum pad diameter for a .008" hole should be a .031" pad. Again, it must be noted that this is a minimum and shouldn't be used unless necessary, or the manufacturer used is very consistent. The recommended size would be at least .002" over the minimum diameter. These example values were based on conventional technology.

        Find internal/external pad dia = Min. AR (.0025") + MFG AR (.009) x 
                  2 + hole dia. Example: (.0025 +.009" x 2 + .070")

The AR should be, at the minimum .002" (annular) larger than the plating for the external pad and, at the minimum .001" larger that the plating for an internal pad. Effectively the plating thickness is .0025–.0030" (specify which to use in your fabrication notes). Use Table 5-6 as a rule of thumb for the AR before adding the MFG AR.

Now the manufacturer annular ring is added (Table 5-8) and becomes part of the pad. The MFG AR is added to account for the manufacturer's errors. These must be added to display the finished pad size.

Using these values, the designer may simply add the hole, and the result is the finished pad.

Table 5-9 is an example using a .031" hole.

Soldered Thru-Holes

Most of the same rules apply to the soldered thru-hole except that the external surfaces must be larger to dissipate heat to avoid problems described in Chapter 3. If possible, for consistency and ease of calculation, the internal pad should be the same as the external, unless a reduced pad is necessary. The reason for this is that the external pad is soldered and the internal pad is not. A soldered thru-hole must also increase in proportion to the lead diameter since a larger lead requires more heat; thus to distribute heat evenly between the lead and the pad, the pad must increase as well.

The pad for the soldered thru-hole has a range of acceptable size. That range is no less than the minimum AR up to 2 times (2 x) the hole size. The rule of thumb for a soldered pad is 2 times the finished hole diameter. Three basic multipliers, which correlate with design requirements, can be used to determine the pad diameter (Table 5-10). Figure 5-8 can be used to determine which calculation to use.

Note

These values are based on the standard component lead material and may change according to material type.

Note

The Designer's Resource software calculates these three values and will display values no less than the minimum AR (includes finished AR & manufacturer AR).

Note

The accompanying software allows you to adjust the "over hole value" (+.010" by default) as well as adjust pads, across the board, for special considerations, and adjust the pad by the copper thickness selection. The printable forms include worksheets for calculating hole and pad.

The Thermal Pad

Thermal connections are features used/required for only soldered pads. Normally used on plane layers or in a solid copper area, they are three or four traces connected to the pad in a + or x shape. The actual traces are known as spokes because of their bicycle spoke appearance. Instead of connecting the plane/solid copper area directly to the hole wall, these spokes are used to reduce the heat sinking affect of the copper areas. A balanced ratio of board copper to component lead metal dictates that the soldered thru-hole have limited copper area, but maintaining adequate area for current-carrying capacity. For this reason the combination of the spoke widths is equivalent to the pad diameter. The thermal pad is the same diameter as other inner-layer pads. The area containing the pad and the spokes is known as the thermal outer diameter. This distance is the inner diameter x 1.5.

The term thermal pad is now a misnomer. The hand tape method used negative planes, and an actual pad was placed. Now with computer-generated images, the pad is no longer used.

Non-Plated Thru-Holes

There are two types of non-plated thru-hole; with a pad and without a pad. It is important to note that a pad is either plated or nonplated. During the plating process, if a pad exists, the hole will plate with copper. If a pad should not be plated, then it must be drilled after the plating process, creating an extra process and additional cost. The NPTH without a pad may be drilled at the same time as the others.

Non-Plated Thru-Holes, with Pad

Non-plated thru-holes (NPTHs) have no plating in the hole that is drilled through the pad. That means there is no additional support to hold the pad to the board besides the normal copper adhesive. For this reason the pad must be larger to help adhere or hold the pad to the board if heated or soldered. IPC specifies that such unsupported pads should have an annular ring of .006"[.152]. This value should be even larger if the pad is soldered.

Non-Plated Thru-Holes, without Pad

The generic NPTH is no more than a hole in a board, with no pad or hole wall plating. These are used for numerous reasons, such as a mounting hole (or screw holes), accessing holes for screw adjustments, or a routing hole for wire. No plating or annular ring requirements are necessary. The general thru-hole is unlike the other holes because it has no plating or soldering considerations.

Mounting Holes

Clearances around mounting holes are larger to compensate for drill tolerance. These holes are not the same as board-to-edge to regular clearance. It is effectively clearance requirements + drill registration + layer registration (if applicable). The drill registration error and the layer registration error are still there, but there is not an image registration, since there is no image. Mounting holes need to be treated differently because of the lack of pads. The manufacturer's annular ring compensates for the misregistration; thus all the errors are retained in the pad area. This means the annular ring, usually reserved for pads, is converted into clearance area.

If the software allows keep-outs, clearance areas around the pads, or some sort of mounting hole clearance attribute, it should be the same as the manufacturer's ring as a general rule.

Aspect Ratio

As explained in Chapter 2, first the minimum hole available must be determined, otherwise a manufacturer will not be able to build the board or the board may be very expensive to build. As mentioned earlier, when discussing capabilities with the manufacturer, use the terms starting or finished aspect ratios and minimum finished drill. Table 5-11 provides a quick reference to finished aspect ratios.

Tip

If the manufacturer can only provide the starting aspect ratio, then find the minimum starting hole and add the "drill over," or the amount the manufacturer drills over the finished hole. Then divide this into the same board thickness to provide the finished aspect ratio (for example, 12:1 starting aspect ratio, in a .125" board = .010" drill). Add drill over [.005"] = .015"; now divide into the board thickness = 8. This is the first part of the aspect ratio 8:1.

Determining What Fabrication/Registration Errors Are Applicable

Although it is best to use the AR value as a minimum with all pads, it becomes an issue when space is a problem. The annular ring consists of

• Drill registration tolerance

• Image registration tolerance

• Layer registration (For multilayers)

These values control many aspects of the board, including

• Board edge

• NPTH pad diameter

• PLTH pad diameter

• Trace to hole clearance

• Trace to cutout clearance

The following images display the affects of image, layer, and drill shifts during the process, accounting for the manufacturing annular ring. Figure 5-9 displays a normal board with the image (copper pad), layer, and drill aligned.

Figure 5-10 is an exploded view of the board displaying each feature of the three features.

Figure 5-11 displays the effects of a layer shift. In this example the inner layer is shifted within an acceptable amount.

Each shift is within acceptable standards (+.003"). Each shift accounts for .003" and in combination add up to .009" of shift. These allowable shifts define the manufacturer's annular ring.

Image registration tolerance is almost always there to some extent. Direct imaging greatly reduces the value, but some will remain.

Lay-up registration is calculated only in multilayer boards. This registration is incurred when multiple layers are stacked together and pressed. For a single/double-sided board, the board is one single piece and cannot move during the process, thus eliminating any registration error.

AR specifications usually includes the layer registration, so when a SS or DS board is done, simply remove that value. This is why it is important to have your manufacturer define these values.

Finding the Current Capacity of a PLTH

To determine the current-carrying capacity of a PLTH, the hole must be laid flat to provide the equivalent of a trace (see Figure 5-14 for an example). This will not be exactly equivalent, but by using the finished hole the value is more than adequate.

        finished hole x Pi = Width
       Example: .030 x 3.14 = .0973

The plating thickness is then matched to an equivalent copper thickness. Common hole wall thickness is .0025–.0028", equivalent to a 2 oz copper. Calculate the current capacity of a 2 oz copper x .0973" wide.

        .0007" = .5 oz, .0014" = 1 oz, .0028" = 2 oz, .0042" = 3 oz

Defining Space/Clearance

Space requirements are defined by either voltage requirements or for mechanical error compensation, or both.

In regard to electrical requirements there are clear multipliers for the internal and external layers. This is a simple calculation and a simple process. In regard to mechanical error compensation, clearances are in addition to the electrical clearances.

Trace to Trace and Trace to Via

These values are approximate to that of the technology requirements. This clearance should be the minimums of the technology requirements or the electrical requirements. Since neither the trace or the via is soldered, there are no solder clearance considerations. Values such as Trace-to-(soldered) Pad and Trace-to-Hole depend on additional requirements, such as registration and soldering clearance.

Trace to Pad (Soldered)

Trace to pad in general requires only the same clearance as the electrical clearance. Because of solder mask registration errors, or "solder mask swell," the external clearances between the soldered pad and the trace need to be larger. This eliminates the possibility of a trace being exposed and possibly shorted when the pad is soldered. In addition, the electrical clearance requirements are not from trace to trace and trace to pad, but also to exposed areas. This requires the electrical clearance to be added to the trace to pad clearance.

The typical setting for a conventional board is .010"[.254] over on mask swell (.005"[.127] per side) and the minimum clearance is .006"[.1524] Average registration error for solder mask is .003"[.0762]. Adding the .003"[.0762] with the .005"[.127] of the mask swell allows a .008"[.2032] of area exposed around a pad.

This then dictates that the Trace-to-Pad clearance is the annular mask swell + mask registration + electrical clearance (as shown inTable 5-12).

Trace-to-Hole

Trace-to-Hole clearance is similar to Trace-to-Pad clearance since it differs from just the standard clearance. A pad and a trace are on the same layer, and when the layer or film is misregistered, both the pad and the trace move together. With a pad and a hole, the manufacturer requires additional room in the pad to account for misregistration between the hole and the layer(s). Thus any registration error is retained within the pad and, internally, the clearance is only the electrical clearance. With the trace to hole clearance, since the hole isn't retained in the pad, the clearance includes the registration error plus the electrical clearance and the plating, since the actual drilled hole is where the measurement is taken from. Table 5-13 may be used to calculate Trace-to-Hole distance.

Only those registration errors that apply need be added. An SS/DS board doesn't have a layer registration error. Only ML boards are pressed together have a possible lay-up error.

An example of a ML board, using conventional technology with a .006" electrical clearance, would look like that shown in Table 5-14.

An example of a DS board, using conventional technology with a .006" electrical clearance, would look like that shown in Table 5-15.

Hole-to-Hole

Hole-to-hole clearance is simple. Same size holes are drilled at the same time and would only need to be separated by the spacing shown in Table 5-16. Because of the tolerances in drilling, drilled holes have the chance of "breaking out" or breaking into each other's space. These values depend on the technology of the drill used, plus additional space to provide additional strength.

Pad to Pad

Pad-to-Pad is not only limited by technology but by the assembly requirements. Large pads that consume large amount of solder and heat usually require a larger soldering iron. This forces clearances on soldered areas to be more as shown in Table 5-17.

Solder Dams

A solder dam is material placed between pads to prevent solder flowing from one pad to another. This is a consideration usually with surface mount components with a fine pitch, or when the pads are very close together. Solder mask or some other type of coating separates large pitch surface mount components. The small gap between surface mount pads and mask swell allows very small amounts of mask to be placed between pads. These limits are controlled by the technology of the manufacturer and the manufacturer's limits. Solder mask minimum width is usually the same as the minimum trace and space. When using a very high technology, such as leading edge or state of the art, different materials may be used for masking when chip size and component size become excessively small.

• Define assembly direction (especially auto assembly).

• Define/determine component direction. For high service boards all I.C. should be in the same direction and oriented the same way.

• Define areas by type.

• Define layers, including.

• Number

• Symmetry (signal plane signal, etc.)

• Layer direction

• Layer type (strictly power, digital, etc.)

• Split planes

• Copy board, cutout, and slot outlines to all plane layers providing copper to edge clearances.

Clearances and Board-to-Edge Clearance

Copper-to-Edge clearance, also known as Board-to-Edge clearance, is a line twice the width of the required clearance that may be used for the border and clearance areas on plane layers. The fabrications notes should instruct the fabricator to cut the board to the center of the line. This is the way the manufacturer functions when creating a route for the board.

Slots

Slots are relatively the same as mounting holes but treated as a board edge. The same clearance values for the board-to-edge clearance (copper-to-edge clearance) apply. Check the table of manufacturer's capabilities to see what the minimum slot shall be. This is based on the minimum radius. The radius is one half of the router bit; thus the slot must be twice the radius (see Table 5-18). The radius width is also determined by the material thickness and based on hardness of the material.

Making Board Edge/Slot Clearance

A problem with many PCB software packages is the oversight in creating a rubber banding cutout/border that will build in clearances on appropriate layers. As shown in Figure 5-15, the inner layer copper will be exposed in a slot, the same as all cut edges of a board unless a clearance area is added to the design. Any copper layer in the design software should have a clearance area between the copper area and any routed edge. This is to prevent the router bit from pulling the copper from inside the board. A technique used in the design software is to use a board outline twice that of the desired clearance. Any slot or board edge should be drawn using this width of line. This line can then be copied to any negative plane layer, providing consistent clearance on all plane layers. A line width twice of the clearance is used in conjunction with a note specifying the manufacturer to route to the center of the board outline.

Note

A negative plane is a plane layer where any colored image is lacking copper and any clear area represents copper.

• Add text to plane layer as to net name (GND, +5 V, etc.).

• Calculate board thickness and determine material availability. Attempt to use predefined or previously used combinations. Or, after design completion, save successful stack-up combinations.

• Add tooling holes, if appropriate.

Tooling

In special cases tooling holes are necessary. Tooling holes are three or more holes placed at the board's extents used for routing special shape boards, such as round boards and some slots. If boards are beyond the normal square or rectangular boards, it is recommended to place tooling holes. Several different sizes are available, but a .125" pin (.126" hole) is used. Placing these holes to the extents of the boards provides stability from twisting during routing.

Fiducials

Fiducials come in several different sizes and shapes. Figure 5-16 shows the old-style fiducials or targets. These are used as targets for auto assembly, and are helpful for manufacturing. It is highly recommended to place at least three (or more) fiducials toward the extents of the board. This helps the manufacturer ensure alignment and is helpful for the designer to verify layer alignment.

• Add datums to all layers or overlay layer. This helps not only to verify alignment after completion but for manufacturing alignment.

• Board part number in copper on bottom side.

• Board revision (in copper or manually marking).

• Layer number (each layer, numbered by layer number, each offset).

• Assembly number (on silkscreen, topside).

• Assembly revision (leave blank area for manual marking).

Initial checks

• Check that power pins are connected correctly on one of each type of part.

• Check that plated-mounting holes are grounded when required.

• Complete placement location and prepare for routing.

Manual Routing

• Route the following types of nets first:

• Most difficult

• Most complex

• Tight fitting nets first

• Very high current (primarily external)

• Very high voltage (primarily internal)

• Sensitive

• Noisy

• Separate analog and digital.

• Route busses.

Auto Routing

• Manually route those items shown in "manual routing" first, if necessary.

• Define attributes that are commonly only to the auto router.

• Define/select "Routine," "Do" file, "Route" file, or "Strategy" file.

• After route completion,

• Manually clean up paths.

• Miter right angle corners.

• Run DRC/design rules to ensure clearances are met.

• Check annular ring.

Component Placement and Routing Methodology

Components are placed primarily in order of function, easing routing requirements. Some boards are designed for aesthetics, where all components are placed in the same orientation, and orientation is also a consideration for assembly ease and auto assembly. (See Chapter 2 for additional information.) Component alignment also eases maintenance/servicing but may increase the complexity of routing. If the board is of low or no maintenance, then component orientation can be overlooked, except for assembly issues.

Figures 5-17 through Figure 5-19 show several methods of routing. A board may use a combination of these styles, depending on the number of layers and component placement. Components may be placed, all in similar orientation, providing consistent pin 1 location, or they may be placed to accommodate routing and reducing vias.

Alternate routing (Figure 5-19) is the simplest form alternating layers per direction. The top layer may be all horizontal lines and the bottom layer all vertical lines, or alternating each layer. Alternate routing is also used in some "noisy" designs to reduce parallelism and crosstalk.

The flip route method (Figure 5-18) is the same as alternate routing but occurs when the connecting pins are mirrored.

Note

Via reduction is important for high frequency design, reducing the number of layer transitions and reduces overall manufacturing cost calculated on number of holes drilled.

Determining Trace Width from Space Available

One controlling factor when determining trace width is space between pads on a connector. Regardless of current requirements, a trace must be routed. After the pads have been defined depending on assembly and serviceability and current requirements have been defined, the trace width is defined, as mentioned earlier in this chapter. If initial trace width will not fit, there are a few options:

• Change connector/components.

• Duplicate layer.

• Increase copper thickness.

• Change from internal layer (if internal) to external layer. (External traces may be smaller than internal.)

• Decrease clearance settings.

Remember that the trace weakness is the smallest width in a trace. If a trace was to break because of current, it will be at the narrowest point or the area with the smallest amount of copper. When tapering or necking up/down, it must be understood that the narrow part is the minimum width and the rest of the trace is a wider line than necessary.

Escape and Fan-Out

Component escape and fan-out are critical to designs and are commonly the areas that determine the trace width (see Figure 5-20). Escape from a component may even determine the number of layers required. A Pin Grid Array (PGA) is one of the most difficult components to fan out, and the designer may even have to have one signal layer for each row of pin from the center. As shown in Figure 5-21, four rows may require three signal layers.

Attempt to route the first row on the bottom layer of the board. This will reduce/eliminate shorts or damage to the traces from soldering.

Wide Line Routing

Wide line routing is a term regarding a trace that is wider than required or the minimum trace width. This is recommended for traces in which

• Surges occur.

• There are unsubstantiated current requirements.

• Trace resistance is in question.

• The trace is constantly on.

• Temperature is high.

Wide line routing is used during routing for these reasons but may be reduced to the minimum when required. The advantage of wide line routing is heat dissipation for traces that have a constant current and have a high temperature expectancy.

Branch Circuits

Circuits do not always carry the same amount of current throughout. There is a source point and possibly several destinations. Each destination may not draw the same amount of current. Therefore, each branch of the same circuit does not necessarily need to be the same width (see Figure 5-22). This can only work if the software supports branch circuits (subnets) and the designer defines each branch separately. Circuits such as ground and Vcc may have high current requirements, but the current cumulative. The cumulative current may be 5 Amps but is divided among five circuits at 1 Amp each. The traces may either fan out from one point with a trace width for only for 1 Amp, or a main branch can carry 5 Amps and then break out into separate 1 Amp traces.

Component Placement for Routing

Components such as connectors, switches, and lights sometimes have placement requirements and should be placed first. Component placement requirements are first determined by auto assembly if used and maintenance requirements. Discrete components such as resistors and capacitors should be placed in line with other components, or with each other to avoid path obstructions and to create routing channels (as shown in Figure 5-23).

Paths can also be predetermined and left clear of components. This allows the following:

• Separation of signals

• Matching lengths

• Reduced bends

• Reduced number of vias

• Reduced layers required

Form or Function

The constant battle in board design is of form or function. Application, board space, assembly, and a little philosophy drive this decision. Auto assembly dictates that the directions of components are placed primarily in the same direction. Manual assembly requires (or it is recommended) that the components be placed somewhat uniformly to avoid confusion during component population. Many companies like boards to be uniform and smooth in appearance. Designers want components to be placed in the best positions for easy routing. Board area requires that components be placed in a manner in which all components can be routed within the confined space using minimal layers. None of these are the only method, but all aspects are combined and considered during component placement. The compromise is placing components in a uniform direction but located to maximize route ability.

Primary Routing Layer

The primary routing layer isn't necessary but helps reduce layers and provides uniformity. SS boards will, of course, have only one side, and that side will be the primary routing layer.

A DS/ML board that is mostly thru-hole should have the bottom side as the primary routing layer. This is to reduce traces under components, provide better accessibility for cuts and jumpers, and alleviate heat and component noise.

A DS/ML board that is mostly surface mount requires the side with the surface mount components to be the primary routing layer. The surface mount components would require a via to connect the component to any other layer, thus making it more practical to use the same layer.

Primary Routing Direction

With an SS board there is no primary routing direction. All directions are required for routing.

With a DS/ML board, it is necessary to alternate directions on each layer, as shown in Table 5-20.

This accomplishes the following two things:

• Reduces parallelism between layers

• Provides horizontal and vertical routing paths

Many auto routers take this initial approach for routing of alternating layers whenever necessary and then removing unnecessary vias. Vias increase the space required between traces but usually shorten the routing path.

Single-Sided Route

A single-sided board is one of the most difficult because of the inability to use vias or change layers. Placement becomes critical, and all parts must be placed strategically with respect to route ability. Wire jumpers may be required to route the board if there isn't adequate space or there is no possible entrance to an area or to a component lead.

Before deciding to design a single-sided board, assembly time for wire jumpers against the additional cost of a double-sided board should be considered. In many cases where cost is critical, single-sided boards are a must.

Routing Bends/Miters

A bend or miter is an angle used in place of 90 degree corners. Traditionally the bend was necessary because the materials could stretch in the x- and/or y-axis, causing breaks in traces.

This stretching or swelling was due to the material properties and lack of humidity controls. With today's higher technology materials and better standards in material storage, stretching and swelling are rare, but the effects are proportional to the trace width. Just as a string is stretched, a wider string takes more than a smaller string of comparable material. Therefore, larger traces, those around and above .006", will feel little effect from any swelling, but traces below that are more susceptible to changes in the material. Even if a designer only designs boards using larger traces, mitering traces is a good practice to help prevent etch pools and ensure spacing consistency throughout designs.

Etch pools are an event that occurs during the manufacturing process when a chemical etchant is used. Higher technology etch processes have all but eliminated this problem. Traces that have 90 degree corners tend to collect etchant, which will continue to eat away at the copper, resulting in a thinner trace width at the corner.

The spacing features presented with bends and miters allow traces to cut diagonally across a board, resulting in additional space or better use of the space available.

Many practices in design are not necessary for low technology boards but are a good practice for designs that may require such practices. If the same rules are used throughout all designs, then the designer will have a good handle on higher technology boards, reducing the learning curve.

Selecting the length and the spacing in a corner (Figure 5-24) comes down to philosophy and application. The easiest way is to start a bend at the first possible moment, which decreases available space (in some instances) while following as closely to other lines in the bend as possible (Figure 5-25).

This depends on application and space availability. Highly populated boards will have tighter, smaller bends than lightly populated boards. Other factors, such as length reduction and spacing for noise, become considerations in higher frequencies. Mitering can be based on trace width and/or grid spacing. Many times the grid spacing used is also based on trace width, so the following is a good rule of thumb:

• .025" for traces under .012"

• .050" bend for traces under .024" to .014"

• .100" bend for traces .049" to .025"

Bus Routing

Many designs contain a group of connections that have similar beginning and end points. They may form a bus. In the schematic, the common thread is not always the same as in the PCB. The schematic's bus normally will be from one single component to individual and vice versa, or similar components, such as relays or several resistors that are of a common area or are going to a common area that are grouped together, creating a bus. Many times they are of a common signal or a common type of signal. Many/most of these buses will follow through to the PCB, and then additional lines that have either a common source, destination, or both will form, to create a bus.

Sensitive and protected signals are the first to be routed, then the bus lines. This is due to the number of lines that are contained, and they create a known amount of lines that will be contended with. Even other lines, not of the same group or area, may be included in the bus in some way to produce a clean path or a conduit of lines.

Caution must be used in the buses since parallel lines commonly cause crosstalk.

Noise, RF, EMF, Crosstalk, and Parallel Lines

There aren't clear guidelines between line length and spacing, along with the signal type. Weak or low voltage signals are susceptible to crosstalk, and "noisy" lines with many spikes and higher frequencies can inject noise into a parallel line that would not appear susceptible to noise. This event is known as saturation.

• Change gates or parts.

If a schematic was generated to help create the PCB, updating the schematic with PCB changes is critical! Any changes made should be reported back to the schematic. Most software packages allow what is known as "gate swapping" or allowing components that have identical parts/gates to be swapped with each other to provide a smoother and easier route.

Placement and Routing Interactivity

Form before function, or function before form? Defining the useable space, fixed placement components, as well as electrical/routing requirements determines the complexity of a board. No matter the spacing requirements, the electrical requirements are the controlling items. The design of the circuits determines the current and the voltage, two of the controlling items of the trace and space. The determination is then made to use thru-hole components or surface mount components from the amount of space available on the board and the area in the enclosure (if applicable). A consideration that is one of the largest factors and usually has the most impact is price.

Components are placed in their necessary position, such as potentiometers, displays, connectors, and mounting holes, and clearance area is determined.

Additional Markings

• ESD symbol

• High voltage warning

ESD labeling is a common practice for boards with components that are susceptible to damage from static discharge or physical contact that emits an electrical discharge. (Contact the ESDA or Electronics Static Discharge Association for additional information at http://www.esda.org.) High voltage warnings labels are a good practice and in some instances (specification and testing specific) are required.

After initial routing is complete and components are fixed, a design rule check, or DRC, is performed, verifying that electrical requirements are met.

• Run DRC/design rules to ensure that clearances are met.

Before polishing a design, it is good practice to ensure that all the rules and attributes are met. The same utility used in the schematic is used in the PCB. The DRC is a utility in most software packages that allows the user to check the design against the settings, attributes, and connections that were defined at the beginning. If clear values are not defined, then the program cannot check them, so it is important that those attributes required are defined. The most basic are as follows:

• Trace clearance (per design, net class, class-to-class and/or layer)

• Trace width (per design, net class, class-to-class and/or layer)

• Board edge

• Component clearance

If the numbers of errors are overwhelming, narrowing the check and troubleshooting one type at a time is recommended.

• Relocate reference designators to their correct position/location/orientation.

After the correct component locations are determined and most everything is in its place, the location of the reference designator (Ref Des) is next. Sometimes the location of the component is determined by the space required by the reference designator. Other times, when the designations are not critical, their locations are left to last and some are just left off. At the very least the designation should be placed under (or on top of) the component and used in the assembly drawing. Commonly an "all or none" approach is used to displaying the designators. It may be acceptable, if a troubleshooting manual will accompany the machine the board will be used in, that an outline of the board and the components with the designators displayed is the only source of locating components. See Chapter 8 for more information on reference designation locations.

• Relabel/renumber reference designators.

Relabeling or renumbering the Ref Des on a board depends on the application. It is strongly recommended that highly serviceable boards should be renumbered. This allows a logical order of components, so component locating is made easy.

The industry standard for renumbering is from the upper left-hand corner to the bottom right-hand. This is relative to reading a page in a book and provides logic and uniformity. This is not always the case and, in some applications, may be completely different.

Double-sided boards pose an additional problem. It is recommended that if all the designations are on the topside, then they be treated as if all the parts are on the top side, and if the designations are on the bottom side, along with the components, then they be treated separately and are renumbered from the upper left in regard to the orientation of the board when read.

Creating a Manufacturing/Fabrication Drawing

• Copy border(s) to drawing layer or include border layer.

• Dimension the board in x- and y-dimensions.

• Hole to edge dimensions (this is used for registration verification for Gerber/drill loading).

• Dimension and tolerance of any cutouts under +/- .005" tolerance.

• Board stack-up, to include the following:

• Layer number

• Layer type

• Layer thickness

• Layer tolerance

• Copper layer type

• Minimum trace width spacing per layer (special cases only)

• Overall board thickness

• Overall board tolerance (Conventional ±10%)

Material Stack-Up

Toward the end of the design process, the numbers of layers have been determined. Along the way these values should be noted and a cross section placed in the fabrication drawing. Chapter 2 details the cross section display of the board with copper and dielectric thickness.

• Drill legend, including

• Finished hole size

• Hole type (plated or nonplated)

• Hole tolerance (holes under .080" +/-.003"; holes over .080" +/- .005"; changes per technology)

• Symbol (correlates with fabrication drawing or Gerber export)

• Load or define fabrication notes, including

• Guidelines or specifications to follow unless otherwise noted (PC class [Quality] and type SS/DS or ML)

• Material used (core and Pre-Preg)

• Is copper thickness specified per table?

• Min. trace width and tolerance (+/-.003" general .001" tight)

• Min. clearance and tolerance (+/-.003" general .001" ?tight)

• Plating per same table (more plating, more plating in hole, increased MFG AR)

• Hole plating minimum of .0002 (usually external plating)

• Finish type: HASL or tin lead (check for availability)

• Hole to pad registration (no breakout allowed)

• Layers to layer 1 registration (+/-.002")

• Overall scale tolerance (+/-.002 per inch. +/-.005" overall).

• Board size tolerance (+/-.005")

• Slot tolerance (+/-.003" to -.005")

• Beveling (if required)

• Electrical test and receipt of official test results. If required by P.O. or prototype only. Continuity of less than 5 ohms per inch. Test at 100 V.

• One or more of the following manufacturing markings (usually placed on the bottom side):

• Cage code (normally used by military contractors)

• Company logo (for identification if additional parts need to be ordered later in time)

• Date code (for board history)

• Lot code (for troubleshooting)

• Electrical test verification marking

• Twist and bow value (.010" def., .007" tight)

• Coupon or x-ray inspection for hole wall quality (one of the most important quality aspects of a board)

• Other

As noted in Chapter 2, a fabrication drawing should, in two or less sheets, contain the following:

• Outline of the board with overall dimensions and a hole to board edge location. This helps align the board edge with the holes in the board and for board dimension checks.

• Fabrication notes— Define the standards for the manufacturer to follow and define other attributes above the standards and those not defined at all by the standards.

• Material stack-up with overall thickness and tolerance—The required overall thickness is a must. If not specified the manufacturer will define the layer and material thickness to their discretion. If layer thickness is not a concern, then this is an option.

• Drill table with tolerances and drill symbols in the board outline—This helps the manufacturer check that the drill sizes are correct and within the designer's requirements. Tolerances are different for different drill ranges.

Most of this information is not required but provides additional information that is recommended. Much of this information, such as the drill and board edge information, is used to compensate for the inconsistency between the software used by the designer and the manufacturer. It is highly recommended that this information be provided, but it might be replaced by simple notes directing the manufacturer to use its own standards or to follow the drill/Gerber data provided. IPC also specifies some tolerances and breakout values, which could reduce the need for drill tolerances.

Some manufacturers provide an "as is" service and view drill symbols and dimensions as redundant information and can provide a quicker turn and less expensive board with less information provided.

Documenting

• Sheet/numbers of sheets

• Load or add information block specifying the following (this information may stay with the board until it is removed from the panel):

• Company name

• Company phone

• Layer name

• Layer number

• Part number

• Revision

• Sheet of sheets

Application Company Specific Information

• Add sheet revision block on first page (fabrication drawing).

• Add sheet revision section (border information).

• Update design information such as the following:

• Date (update every time this file is finished, changed, or modified)

• Designed by (designer name)

• Engineer (electrical engineer or the schematic's entry person)

• Checked by (QC, final, or engineer's name)

• Add sheet revision block on first page (Fabrication drawing).

Check Plots (not required)

• Print each layer w/o border to scale.

• Inspect for the following:

• Sheet layer numbers

• Datums

• ESD symbol

• HV note

• Tooling

• Pin 1 identification

• Mounting hole locations

• Board size and clearance

• Mechanical support

• Hardware clearance

• Stack-up thickness

Approval

• PCB approval from engineer.

• Implement any redlines.

• Generate netlist from schematic again.

• Run DRC again and run compare netlist.

Output

• Set up Gerber output files or set up database export.

• Export the following (in 274-X):

• All layer separately

• Required silk screen layers

• Top and bottom solder mask separately

• Fabrication drawing with symbols

• Drill file (in ASCII format, leading suppression)

• Load Gerbers in a CAM/CAD viewer and inspect for consistency with original design.