In modern pcb design, maintaining signal integrity relies on a stable transmission path. Proper impedance control prevents signal reflection and ensures stable performance across your board. This article explores why pcb impedance control is essential, where discontinuities typically occur during pcb layout, and how targeted optimizations improve overall channel quality.
Why do we need pcb impedance control, how do we achieve it, and which aspects require adjustments? The simulation results below tell the story—showing schematics with and without impedance matching.
When impedance mismatch occurs across a transmission link, signals reflect at points of impedance discontinuity. These reflected signals combine with original signals, resulting in waveform anomalies like overshoot, undershoot, ringing, and glitches. Heavy reflection can cause false sampling at the receiver, compromising high-speed system stability.
Effective impedance control requires precise stackup planning. Before routing your high-speed signals, make sure to test your trace impedance with our free online calculator to determine the exact trace width and spacing needed.
From the IC package interior to PCB traces and receiver ICs, high-speed links contain multiple regions vulnerable to impedance mismatch. Common risk areas include:
Impedance discontinuities often occur near IC package pads. While design space here is limited, keeping thin traces short and adding ground cutouts (anti-pads) under adjacent layers can slightly raise impedance—a approach often seen in PCIe Gen5 design guidelines.
Impedance shifts also happen after signal lines exit the IC through capacitors, resistors, vias, and connectors. TDR data clearly demonstrates the difference before and after optimization.
During length matching, inevitable small serpentines on differential pairs can trigger local impedance disruptions. Length compensation segments should be placed in areas with controlled impedance environments, continuous reference planes, and safe distances from sensitive structures like vias or pads. For regions with structural discontinuities, combine topology planning with SI simulation for co-optimization rather than blindly adding serpentine traces along continuous mainlines.
Disrupted return paths cause impedance drops and ground bounce. When high-speed signals change layers without nearby ground stitching vias, returning current is forced to detour. This increases loop area, parasitic inductance, electromagnetic field shifts, crosstalk, EMI risks, and impedance mismatch.
The diagram below shows an impedance jump caused by a reference plane discontinuity. When traces cross reference plane splits, slots, or other discontinuous regions, the original return path is disrupted. This alters the local transmission line structure, creating impedance mismatch and additional signal integrity risks during pcb layout.
The diagram below shows an impedance jump caused by a stub.
The points mentioned above are mostly locations where impedance discontinuities occur along the link. Below is a data comparison of an entire high-speed differential transmission line before and after optimization. The link includes various impedance discontinuity points, such as IC pin output pads, layer-change vias, capacitors, load-end connectors, and stubs.
By optimizing discontinuous impedance structures within the link—including pads, vias, passive components, connectors, and stubs—local signal reflections are reduced, and the channel's return loss performance is significantly improved. In this case, after the impedance structures were optimized, the channel's insertion loss also improved, demonstrating that mitigating severe structural discontinuities helps enhance the overall performance of high-speed channels in pcb design.
Proper pcb design requires systematic approaches across different elements. The following sections outline practical optimization workflows for passive components (based on 4-layer 1.6mm stackups), vias, and length-matching techniques essential for modern pcb layout:
(Note: The following optimization case uses a 4-layer, 1.6 mm total thickness PCB as an example. Actual impedance cannot be determined solely by total board thickness; it must be calculated and verified using dielectric thickness, copper thickness, material Dk, trace width/spacing, and target impedance.)
