In power supply design, there is a common engineering misconception regarding the selection of the LDO output capacitor: when faced with issues like high output ripple or poor load transient response, many hardware engineers simply resort to increasing capacitance—upgrading from 10µF to 47µF, then to 220µF, or even paralleling multiple capacitor types at the output. From an energy storage perspective, a larger capacitance supplies more transient charge for the same voltage variation. It seems logical that continually increasing capacitance would indefinitely improve output stability.
However, practical engineering often presents a counterintuitive reality. Increasing the capacitance of the LDO output capacitor may not improve stability; instead, it can trigger oscillations, produce periodic voltage fluctuations, or even cause system resets. The root cause is that an LDO is not a simple linear voltage regulator—it is fundamentally a closed-loop control system. The output capacitor does not merely filter noise and store energy; it is an active component of the feedback control loop. Incorrect parameter selection directly compromises overall system stability.
A standard LDO design consists of a reference voltage source, an error amplifier, a power pass transistor, a feedback network, and an output capacitor. Its regulation mechanism works as follows: when the output voltage strays from its target, the feedback network detects the error and feeds it into the error amplifier. The amplifier then adjusts the conduction level of the power transistor to tune the output current and bring the voltage back to target. This regulation cycle inherently involves a response time lag.
When a step load change occurs—such as a microcontroller switching from sleep mode to full operation, causing the load current to jump from 10mA to 500mA—the LDO cannot instantly adjust its output current due to loop bandwidth limitations. The immediate current deficit is supplied entirely by discharging the LDO output capacitor. Therefore, increasing capacitance theoretically delivers more transient charge and improves transient load response. However, capacitance cannot be increased infinitely because it dictates loop dynamic behavior and directly affects stability margins.
（LDO Architecture & Feedback Control Loop. Source: Flywing Tech）
In a simplified small-signal model, the output capacitor and the equivalent output load impedance form an output pole, whose frequency is expressed as:
fpole = 1 / (2 × π × ROUT × COUT)
Assuming an output equivalent resistance of 0.1Ω: a 10µF capacitor creates an output pole at approximately 159 kHz, whereas increasing the capacitor to 100µF shifts the pole down to roughly 15.9 kHz. This calculation illustrates how capacitance influences pole placement; in actual practice, loop poles are also shaped by the pass element, error amplifier, feedback network, and internal compensation circuits.
Within any robust power supply design, the output capacitor and its equivalent series resistance (ESR) alter the location of output poles and zeros, dictating crossover frequency and phase margin. As capacitance increases, the output pole moves to lower frequencies, potentially reducing loop crossover frequency or degrading phase margin. Whether this induces oscillation depends on internal compensation, capacitor ESR, load conditions, and phase margin reserves.
（COUT Changes the Output Pole）
Because different topologies utilize distinct internal compensation schemes, the requirements for the LDO output capacitor vary significantly across devices.
Older architectures rely heavily on the ESR of the output capacitor to introduce a zero into the loop function. This zero cancels phase lag introduced by low-frequency poles, thereby preserving phase margin:
fzero = 1 / (2 × π × RESR × COUT)
Replacing the output stage with an ultra-low ESR MLCC pushes this ESR zero to much higher frequencies, removing the necessary phase compensation and potentially causing loop instability or severe oscillation.
Modern LDO design techniques frequently feature internal compensation structures that eliminate strict reliance on ESR, making them fully compatible with low-ESR MLCCs. Nevertheless, capacitance cannot be scaled up without limit. Datasheets still impose recommended maximum capacitance limits because an oversized capacitor shifts loop dynamics, prolongs startup times, and slows fault recovery.
Beyond loop stability issues, an excessively large ldo output capacitor introduces secondary system-level risks.
During power-up, charging the capacitor requires an inrush current governed by:
Iinrush = COUT × (dVOUT / dt)
For instance, charging a 470µF capacitor to 3.3V within 10ms demands an average inrush current of roughly 155mA. If this approaches the current limit threshold while simultaneously supplying load current, the LDO may enter current limit mode or fail to start up entirely.
The total charge transferred during startup is defined by:
Q = COUT × VOUT
When using soft-start or constant-current limiting mechanisms, a high charge requirement extends startup duration. In systems lacking robust current limiters, large capacitance places severe transient demands on the upstream rail. In an unoptimized power supply design, this inrush can pull down the primary voltage rail and trigger unexpected upstream power-good faults or system resets.
Proper component selection requires following datasheet guidelines rather than blindly increasing capacitance values:
The core principle for selecting an LDO output capacitor is not "the larger, the better," but rather choosing parameters tailored to operating conditions within specified stability bounds. The output capacitor plays a dual role in energy storage and loop compensation. Blindly increasing capacitance can introduce unexpected loop instability and startup faults. Mastering proper selection alongside a clean LDO layout ensures a reliable, high-performance power supply design.
