How to Design an H-Bridge Motor Driver: Circuit & PCB Layout Guide

1. Overview of H-Bridge Drive Circuits

An H-bridge drive circuit is one of the most widely used basic topologies in DC motor drive systems. Its core structure consists of four independently controlled MOSFETs arranged as a bridge. By controlling different switching combinations, the circuit can control the current direction and achieve forward rotation, reverse rotation, speed control, and braking of a DC motor. The topology resembles the letter “H,” which is where the name H-bridge comes from.

This article provides a systematic analysis of the key considerations in H-bridge circuit design, covering device characteristics, high-side driving principles, bootstrap circuit design, and PCB Layout guidelines. It focuses on the essential aspects from circuit design to board-level implementation, providing practical guidance for DC motor driver design and optimization. 

(H-Bridge Circuit Topology)

2. Key Device Characteristics and Selection

2.1 MOSFET Body Diode Characteristics

Inside an N-channel power MOSFET, the source and drain are N-type semiconductor regions, while the body region is made of P-type semiconductor material. This structure forms two PN junctions. Since the source is normally shorted to the body, the source-body PN junction remains at zero bias and does not function as a diode. Only the drain-body PN junction operates normally, forming the built-in body diode.

This characteristic is common to power MOSFETs and is also the physical basis for the reverse-parallel diode shown in MOSFET symbols used in circuit simulation models.

2.2 Function and Selection of Freewheeling Diodes

A DC motor is a typical inductive load, meaning that its current cannot change instantaneously. When the MOSFETs in an H-bridge switch rapidly between states, sudden changes in the motor winding current can generate high-voltage back-EMF spikes, which may damage the MOSFETs or cause abnormal circuit operation.

A freewheeling diode is connected in parallel with the MOSFET drain and source. Its main functions include:

• Providing a freewheeling path: When the MOSFET turns off, the diode provides a closed-loop path for the residual current in the motor winding, preventing high-voltage spikes caused by forced current interruption.
• Protecting the devices from overvoltage: The diode clamps the back-EMF amplitude and isolates the power devices from voltage spikes, reducing the risk of device damage.
• Improving electromagnetic performance: In high-frequency switching applications, the diode helps suppress electromagnetic interference (EMI), reduce operating noise, and improve system stability.

The MOSFET's built-in body diode can provide basic freewheeling functionality, but its relatively high forward voltage, long reverse-recovery time, and slow switching response make it unsuitable for high-frequency and high-current applications.

In practical designs, an external Schottky diode is commonly connected in parallel as a dedicated freewheeling device. Its short reverse-recovery time and low forward voltage can significantly reduce freewheeling losses and improve circuit reliability.

(Freewheeling diode connected in parallel with an upper-arm MOSFET)

2.3 Key MOSFET Selection Parameters

When selecting power MOSFETs for an H-bridge motor driver, four parameters should be considered carefully:

1. Drain-source breakdown voltage (VDS): The rating should be 1.5 to 2 times higher than the supply voltage to provide sufficient safety margin for back-EMF spikes.
2. Continuous drain current (ID): The rating should exceed both the motor's rated current and stall current, with additional margin based on the thermal design.
3. On-resistance (RDS(on)): This parameter directly determines conduction losses and device heating. For MOSFETs with the same voltage rating, a lower RDS(on) generally results in higher system efficiency.
4. Gate charge (Qg): This parameter reflects MOSFET switching characteristics. A lower Qg generally results in lower switching losses, but it must be properly matched to the driving capability of the gate driver IC. 

3. High-Side Driving and Bootstrap Circuit Design

3.1 Differences Between High-Side and Low-Side Driving

Based on their positions in the H-bridge topology, MOSFETs can be divided into high-side and low-side devices. The high-side MOSFET is connected between the power supply and the load, while the low-side MOSFET is connected between the load and ground.

The fundamental condition for turning on a MOSFET is that the gate-source voltage must exceed its threshold voltage: VGS > VGS(th)

The source of a low-side MOSFET is connected to ground, so its potential remains fixed. Applying the appropriate drive voltage to the gate is therefore sufficient to turn it on, making the drive circuit relatively simple.

The source of a high-side MOSFET is connected to the load. Its potential changes dynamically with the switching state and remains above ground. As a result, a conventional drive voltage cannot provide sufficient gate-source voltage. A dedicated circuit is required to generate a gate-drive voltage higher than the supply voltage.

A bootstrap circuit is currently one of the most common low-cost solutions for high-side MOSFET driving. 

3.2 How the Bootstrap Circuit Works

A bootstrap circuit consists of a bootstrap diode and a bootstrap capacitor and operates together with the gate driver IC. Taking a half-bridge topology as an example, its operation can be divided into two stages:

1.Charging stage: When the low-side MOSFET is turned on, the source potential of the high-side MOSFET is pulled close to ground. The power supply charges the bootstrap capacitor through the bootstrap diode, causing the capacitor voltage to approach the supply voltage and storing the required energy.

(Bootstrap capacitor charging)

2.Discharge and drive stage: After the low-side MOSFET turns off, the high-side source potential rises. The stored charge in the bootstrap capacitor raises the gate voltage to approximately “source voltage + supply voltage,” providing sufficient gate-source voltage to fully turn on the high-side MOSFET.At this point, the bootstrap diode becomes reverse-biased, preventing the high-voltage charge from flowing back into the preceding circuit and protecting the driver stage.

(Bootstrap capacitor discharge)

3.3 Bootstrap Circuit Design Considerations

The bootstrap capacitor continuously discharges while the high-side MOSFET is on, causing the gate-source voltage to gradually decrease. If the voltage becomes too low, the MOSFET may not turn on completely, resulting in increased power dissipation and heating.

The following points should therefore be considered during design:

• Place the bootstrap capacitor close to the BOOT and SW pins of the gate driver IC. Keep the traces short and wide to minimize parasitic inductance.
• A Schottky diode is preferred for the bootstrap diode because it provides low forward voltage and low reverse-recovery losses.
• Avoid keeping the high-side MOSFET continuously on for an extended period. Make sure the capacitor has sufficient time to recharge during the switching cycle.
• Select an appropriate bootstrap capacitor value to balance drive duration and switching response. 

4. PCB Layout Design Guidelines

PCB Layout directly determines the electromagnetic compatibility, thermal performance, and operating reliability of an H-bridge circuit. It is a critical step in converting the circuit design into a practical hardware implementation.

The main PCB Layout objectives are to minimize parasitic inductance in the power loop, optimize thermal paths, isolate high-power and low-level signals, and establish a low-impedance grounding system.

4.1 Overall Layout Principles

The layout should follow the principles of functional partitioning and signal flow. The PCB can be divided into three independent areas: the power section, driver section, and logic control section.

• Power section: Place MOSFETs, freewheeling diodes, input filtering capacitors, current-sense resistors, and other high-current components close to the motor output connector to shorten the power path.
• Driver section: Place the gate driver IC, bootstrap circuit, and gate resistors close to the power MOSFETs to minimize the gate-drive loop.
• Logic section: Place the MCU, interface circuits, sensing circuits, and other low-power components away from high-current switching nodes to prevent noise coupling.

4.2 Power Loop Design

The power loop is one of the main sources of parasitic inductance and switching noise. The key design objective is to minimize the loop area.

1. Keep the core loop compact: The main power loop consists of: Power input → high-side MOSFET → motor → low-side MOSFET → ground → input capacitor. The loop area should be kept as small as possible. Arrange the MOSFETs closely together and avoid long traces and unnecessary bends.
2. High-current routing: Use wide copper traces or copper pours for high-current paths. With 1 oz copper, a current-carrying capacity of approximately 1 A/mm of trace width can be used as a basic estimate. Where appropriate, use both the top and bottom copper layers and connect them with stitching vias to reduce impedance and inductance.
3. Place filtering capacitors close to the power devices: Large electrolytic capacitors should be paralleled with high-frequency ceramic capacitors and placed close to the MOSFET source pins. Keep the distance within 0.5 cm. Connect the capacitor pads directly to the power and ground planes using multiple vias to minimize parasitic effects introduced by traces. 

4.3 Gate-Drive Loop Design

Parasitic parameters in the gate-drive loop can affect switching speed and may even cause gate oscillation. The following design requirements should be met:

• Keep the trace from the gate driver output pin to the MOSFET gate as short and straight as possible. The recommended length is within 1 cm, with a trace width of approximately 15–20 mil.
• Place the gate series resistor and gate pull-down resistor close to the MOSFET gate pin to suppress switching oscillation.
• Connect the return path of the gate-drive signal directly to the corresponding MOSFET source to avoid ground-bounce noise caused by a long shared ground path.
• Avoid routing gate-drive traces parallel to power traces for long distances. Maintain a spacing of at least 3 mm to reduce coupling interference. 

4.4 Grounding and EMC Design

Grounding is critical for suppressing electromagnetic interference and preventing ground-bounce noise.

1. Separate grounds with a single-point connection: Divide the system ground into power ground (PGND) and signal ground (DGND/AGND). Power ground carries high-current switching loops, while signal ground is used only for logic and sensing circuits. Connect the two grounds at a single point near the input filtering capacitor to prevent voltage drops caused by high currents in the ground plane from affecting sensitive signals.
2. Use a complete ground plane: For four-layer and multilayer boards, a dedicated internal ground plane is preferred to provide the shortest return path for signals. For two-layer boards, use a grid-based ground pour to reduce grounding impedance.
3. Shield the switching node: The MOSFET switching node (SW) is a strong dv/dt noise source. Keep this trace short and minimize its copper area to prevent antenna effects. Sensitive signal traces and crystal oscillator traces should be routed away from this area. Where necessary, surround the sensitive traces with ground traces for additional shielding.

4.5 Thermal Design

MOSFETs and freewheeling diodes are the main heat-generating components. Proper thermal design directly determines the long-term reliability of the system.

• Copper-pour cooling: Connect the MOSFET source, drain, and thermal pads to large copper areas to provide the primary heat dissipation path.
• Thermal via arrays: Place a dense array of thermal vias beneath the thermal pads of power devices, with a recommended via diameter of approximately 0.3 mm, to transfer heat to the bottom or internal copper layers. Filled vias or copper-filled vias can further improve thermal conductivity.
• Reserve space for heat sinks: For high-power applications, reserve mounting holes and sufficient space for a heat sink. Use thermal grease or thermal pads between the device and heat sink.
• Thermally symmetrical layout: When multiple devices are connected in parallel or the bridge arms are arranged symmetrically, ensure that their thermal paths are also balanced to prevent localized overheating. 

5. Engineering Example — BTN7971B High-Power H-Bridge Motor Driver Module

This section uses a high-power H-bridge motor driver module based on the Infineon BTN7971B as an engineering example. The module is designed to drive high-power brushed DC motors and represents a practical implementation of the H-bridge drive principles discussed above.

The design is analyzed from two perspectives: schematic design and PCB Layout.

5.1 Schematic Design

5.1.1 Overall Architecture

The module uses the Infineon BTN7971B half-bridge driver IC as its core power device. Each IC integrates power MOSFETs, gate-drive circuitry, freewheeling diodes, and protection circuitry, eliminating the need for additional external gate-driver and bootstrap circuits and significantly simplifying the peripheral circuit design.

• Rated input voltage: 6–28 V, with a recommended operating voltage not exceeding 35 V.
• PWM input frequency: 1 kHz–10 kHz. Excessively high frequencies increase switching losses and can cause severe device heating.
• Maximum peak current per channel: Up to 90 A, provided that adequate thermal management is implemented. 

5.1.2 Main Power Loop Design

Each complete H-bridge consists of two BTN7971B ICs, which form the high-side and low-side half-bridges respectively. The power supply is connected to the VCC pins of the ICs.

A 4.7 μF/50 V ceramic decoupling capacitor is placed in parallel at the power input of each IC to filter high-frequency switching noise. Multiple 220 μF/35 V aluminum electrolytic capacitors are placed at the main power input, providing a total filtering capacitance of 660 μF per channel to effectively suppress bus-voltage fluctuations during motor startup, shutdown, and direction reversal.

The VS pin of the IC is the power output and is directly connected to the motor winding output connector. 

5.1.3 Signal and Control Circuit Design

• Dual input interfaces: Two signal-input options are provided: a conventional Dupont-style pin header and a 0.5 mm pitch FPC connector, supporting different installation and wiring requirements.
• Logic-level compatibility and signal isolation: Input signals first pass through an SN74LV125 buffer for isolation and level conversion. This supports both 3.3 V and 5 V MCU logic levels while preventing noise from the power stage from feeding back into the control circuit and protecting the main controller.
• Input protection: A 4.7 kΩ current-limiting resistor is connected in series with the signal input path. The input port has a high-impedance characteristic, limiting current under abnormal operating conditions and preventing reverse overcurrent from damaging the MCU or buffer IC.
• Shared enable control: The two half-bridge driver ICs share a single EN enable signal. The enable pins are pulled down to ground through 4.7 kΩ resistors, so the module remains disabled by default after power-up, improving startup safety and preventing unintended operation.
• Current-sensing circuit: Each driver provides a current-sense output pin connected through a current-limiting resistor and an RC filtering network. The resulting analog voltage is proportional to the motor current and can be sampled by the MCU for overcurrent protection and closed-loop current control. 

5.1.4 Power and Auxiliary Circuits

The motor power supply is converted to a +5 V system supply through an MC78L05 linear regulator, which powers the buffer IC, status LEDs, and other auxiliary circuits.

A 100 nF ceramic decoupling capacitor is placed at both the input and output of the regulator to suppress supply ripple. An onboard power indicator LED is connected in series with a current-limiting resistor to provide a visual indication of the module's power status.

5.2 PCB Layout Design

5.2.1 Power Loop Optimization

• Minimize loop area: The main power loop consists of: Power input → BTN7971B high-side → motor output → BTN7971B low-side → ground → input filtering capacitor. A large-area solid copper pour is used to minimize the loop area, reduce parasitic inductance, and suppress switching voltage spikes.
• High-current carrying design: The power path uses copper pours on both the top and bottom layers, connected through dense stitching vias. This improves current-carrying capability, limits temperature rise under high-current conditions, and enhances heat dissipation. The current-carrying capacity is calculated based on the 1 A/mm guideline for 1 oz copper.
• Place filtering capacitors close to the IC: A 4.7 μF high-frequency decoupling capacitor is placed directly next to the power pins of each BTN7971B. The capacitor pads are connected directly to the power and ground planes through vias. Large electrolytic capacitors are also placed close to the power input of the power IC to maximize filtering performance.

5.2.2 Signal Routing Design

• Control signals such as PWM and EN should be routed as short and straight as possible from the input connector to the buffer IC and then to the driver IC, avoiding unnecessary routing. Maintain a spacing of at least 3 mm between signal and power traces and avoid long parallel runs to reduce noise coupling.
• Current-sense signal traces should be routed close to ground traces, while the RC filtering components should be placed close to the current-sense pins of the IC to improve signal stability and noise immunity.
• Since the gate-drive circuit is integrated into the IC, there are no external gate-drive traces. This significantly reduces the risk of gate oscillation, allowing the PCB Layout to focus primarily on maintaining a low-impedance ground return around the IC. 

5.2.3 Thermal and Grounding Design

• Thermal design: The exposed thermal pad of the BTN7971B is directly connected to a large copper area to serve as the primary heat-dissipation path. A dense thermal via array is placed beneath the pad to transfer heat to the bottom copper layer and improve thermal performance. Space for a heat sink is also reserved on the board. For continuous high-current operation, an additional heat sink can be installed to further improve current-handling capability.
• Grounding design: The power ground and signal ground are separated into different areas. Power ground carries the high-current switching loop, while signal ground is used only for control and current-sensing circuits. The two grounds are connected at a single point near the input filtering capacitor to prevent ground-bounce noise from the high-current path from interfering with sensitive signal circuits. Large-area ground pours are used throughout the board to reduce overall grounding impedance.